View R5F104JGA_8974566.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

r01ds0053ej0330 rev. 3.30 page 1 of 208 aug 12, 2016 rl78/g14 renesas mcu true low power platform (as low as 66 a/mhz, and 0.60 a for rtc + lvd), 1.6 v to 5.5 v operation, 16 to 512 kbyte flash, 44 dmips at 32 mhz, for general purpose applications datasheet 1. outline 1.1 features ultra-low power consumption technology ?v dd = single power supply voltage of 1.6 to 5.5 v which can operate a 1.8 v device at a low voltage ? halt mode ?stop mode ? snooze mode rl78 cpu core ? cisc architecture with 3-stage pipeline ? minimum instruction execution time: can be changed from high speed (0.03125 s: @ 32 mhz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 s: @ 32.768 khz operation with subsystem clock) ? multiply/divide/multiply & a ccumulate instructions are supported. ? address space: 1 mb ? general-purpose registers: (8-bit register 8) 4 banks ? on-chip ram: 2.5 to 48 kb code flash memory ? code flash memory: 16 to 512 kb ? block size: 1 kb ? prohibition of block erase and rewriting (security function) ? on-chip debug function ? self-programming (with boot swap function/flash shield window function) data flash memory ? data flash memory: 4 kb and 8 kb ? back ground operation (bgo): instructions can be executed from the program memory while rewriting the data flash memory. ? number of rewrites: 1,000,000 times (typ.) ? voltage of rewrites: v dd = 1.8 to 5.5 v high-speed on-chip oscillator ? select from 64 mhz, 48 mhz, 32 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 6 mhz, 4 mhz, 3 mhz, 2 mhz, and 1 mhz ? high accuracy: 1.0% (v dd = 1.8 to 5.5 v, t a = -20 to +85c operating ambient temperature ?t a = -40 to +85c (a: consumer applications, d: industrial applications) ?t a = -40 to +105c (g: in dustrial applications) power management and reset function ? on-chip power-on-reset (por) circuit ? on-chip voltage detector (lvd) (select interrupt and reset from 14 levels) data transfer controller (dtc) ? transfer modes: normal transfer mode, repeat transfer mode, block transfer mode ? activation sources: activated by interrupt sources. ? chain transfer function event link controller (elc) ? event signals of 19 to 26 types can be linked to the specified peripheral function. serial interfaces ? csi: 3 to 8 channels ? uart/uart (lin-bus supported): 3 or 4 channels ?i 2 c/simplified i 2 c: 3 to 8 channels timer ? 16-bit timer: 8 to 12 channels (timer array unit (tau): 4 to 8 channels, timer rj: 1 channel, timer rd: 2 channel s, timer rg: 1 channel) ? 12-bit interval timer: 1 channel ? real-time clock: 1 channel (c alendar for 99 years, alarm function, and clock correction function) ? watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) a/d converter ? 8/10-bit resolution a/d converter (v dd = 1.6 to 5.5 v) ? analog input: 8 to 20 channels ? internal reference voltage (1.45 v) and temperature sensor d/a converter ? 8-bit resolution d/a converter (v dd = 1.6 to 5.5 v) ? analog output: none or up to two channels ? output voltage: 0 v to v dd ? real-time output function comparator ? none or up to two channels ? operating modes: comparator high-speed mode, comparator low-speed mode, window mode ? the external reference voltage or internal reference voltage can be selected as the reference voltage. i/o port ? i/o port: 26 to 92 (n-ch open drain i/o [withstand voltage of 6 v]: 2 to 4, n-ch open drain i/o [v dd withstand voltage/ev dd withstand voltage]: 10 to 28) ? can be set to n-ch open drain, ttl input buffer, and on- chip pull-up resistor ? different potential interface: can connect to a 1.8/2.5/3 v device ? on-chip key interrupt function ? on-chip clock output/ buzzer output controller others ? on-chip bcd (binary-coded decimal) correction circuit remark the functions mounted depend on the product. see 1.6 outline of functions . r01ds0053ej0330 rev. 3.30 aug 12, 2016
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 2 of 208 aug 12, 2016 rom, ram capacities the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f104xd (x = a to c, e to g, j, l): start address fe900h r5f104xe (x = a to c, e to g, j, l): start address fe900h r5f104xj (x = f, g, j, l, m, p): start address f9f00h r5f104xl (x = g, l, m, p): start address f3f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) . flash rom data flash ram rl78/g14 30 pins 32 pins 36 pins 40 pins 192 kb 8 kb 20 kb ? ? ? r5f104eh 128 kb 8 kb 16 kb r5f104ag r5f104bg r5f104cg r5f104eg 96 kb 8 kb 12 kb r5f104af r5f104bf r5f104cf r5f104ef 64 kb 4 kb 5.5 kb note r5f104ae r5f104be r5f104ce r5f104ee 48 kb 4 kb 5.5 kb note r5f104ad r5f104bd r5f104cd r5f104ed 32 kb 4 kb 4 kb r5f104ac r5f104bc r5f104cc r5f104ec 16 kb 4 kb 2.5 kb r5f104aa r5f104ba r5f104ca r5f104ea flash rom data flash ram rl78/g14 44 pins 48 pins 52 pins 64 pins 512 kb 8 kb 48 kb note ? r5f104gl ? r5f104ll 384 kb 8 kb 32 kb ? r5f104gk ? r5f104lk 256 kb 8 kb 24 kb note r5f104fj r5f104gj r5f104jj r5f104lj 192 kb 8 kb 20 kb r5f104fh r5f104gh r5f104jh r5f104lh 128 kb 8 kb 16 kb r5f104fg r5f104gg r5f104jg r5f104lg 96 kb 8 kb 12 kb r5f104ff r5f104gf r5f104jf r5f104lf 64 kb 4 kb 5.5 kb note r5f104fe r5f104ge r5f104je r5f104le 48 kb 4 kb 5.5 kb note r5f104fd r5f104gd r5f104jd r5f104ld 32 kb 4 kb 4 kb r5f104fc r5f104gc r5f104jc r5f104lc 16 kb 4 kb 2.5 kb r5f104fa r5f104ga ? ? flash rom data flash ram rl78/g14 80 pins 100 pins 512 kb 8 kb 48 kb note r5f104ml r5f104pl 384 kb 8 kb 32 kb r5f104mk r5f104pk 256 kb 8 kb 24 kb note r5f104mj r5f104pj 192 kb 8 kb 20 kb r5f104mh r5f104ph 128 kb 8 kb 16 kb r5f104mg r5f104pg 96 kb 8 kb 12 kb r5f104mf r5f104pf
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 3 of 208 aug 12, 2016 1.2 ordering information figure 1 - 1 part number, memory size, and package of rl78/g14 fields of application: a: consumer applications, t a = -40 to +85 c d: industrial applications, t a = -40 to +85 c g: industrial applications, t a = -40 to +105 c packaging specification #30: tray (lfqfp, lqfp) #u0: tray (hwqfn, wflga, flga) #v0: tray (lfqfp, lqfp, lssop) #50: embossed tape (lfqfp, lqfp) #w0:embossed tape (hwqfn, wflga, flga) #x0: embossed tape (lfqfp, lqfp, lssop) r 5 f 1 0 4 l e a x x x f b # v 0 package type: sp: lssop, 0.65 mm pitch fp: lqfp, 0.80 mm pitch fa: lqfp, 0.65 mm pitch fb: lfqfp, 0.50 mm pitch na:hwqfn, 0.50 mm pitch la: wflga, 0.50 mm pitch flga, 0.50 mm pitch rom number (omitted with blank products) rom capacity: a: 16 kb c: 32 kb d: 48 kb e: 64 kb f: 96 kb g: 128 kb h: 192 kb j: 256 kb k: 384 kb l: 512 kb part no. pin count: a: 30-pin b: 32-pin c: 36-pin e: 40-pin f: 44-pin g: 48-pin j: 52-pin l: 64-pin m: 80-pin p: 100-pin rl78/g14 memory type: f : flash memory renesas mcu renesas semiconductor product
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 4 of 208 aug 12, 2016 note for the fields of application, refer to figure 1 - 1 part number, memory size, and package of rl78/g14 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website. (1/5) pin count package fields of application note ordering part number 30 pins 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) a r5f104aaasp#v0, r5f104acasp#v0, r5f104adasp#v0, r5f104aeasp#v0, r5f104afasp#v0, r5f104agasp#v0 r5f104aaasp#x0, r5f104acasp#x0, r5f104adasp#x0, r5f104aeasp#x0, r5f104afasp#x0, r5f104agasp#x0 d r5f104aadsp#v0, r5f104acdsp#v0, r5f104addsp#v0, r5f104aedsp#v0, r5f104afdsp#v0, r5f104agdsp#v0 r5f104aadsp#x0, r5f104acdsp#x0, r5f104addsp#x0, r5f104aedsp#x0, r5f104afdsp#x0, r5f104agdsp#x0 g r5f104aagsp#v0, r5f104acgsp#v0, r5f104adgsp#v0, r5f104aegsp#v0, r5f104afgsp#v0, r5f104aggsp#v0 r5f104aagsp#x0, r5f104acgsp#x0, r5f104adgsp#x0, r5f104aegsp#x0, r5f104afgsp#x0, r5f104aggsp#x0 32 pins 32-pin plastic hwqfn (5 5 mm, 0.5 mm pitch) a r5f104baana#u0, r5f104bcana#u0, r5f104bdana#u0, r5f104beana#u0, r5f104bfana#u0, r5f104bgana#u0 r5f104baana#w0, r5f104bcana#w0, r5f104bdana#w0, r5f104beana#w0, r5f104bfana#w0, r5f104bgana#w0 d r5f104badna#u0, r5f104bcdna#u0, r5f104bddna#u0, r5f104bedna#u0, r5f104bfdna#u0, r5f104bgdna#u0 r5f104badna#w0, r5f104bcdna#w0, r5f104bddna#w0, r5f104bedna#w0, r5f104bfdna#w0, r5f104bgdna#w0 g r5f104bagna#u0, r5f104bcgna#u0, r5f104bdgna#u0, r5f104begna#u0, r5f104bfgna#u0, r5f104bggna#u0 r5f104bagna#w0, r5f104bcgna#w0, r5f104bdgna#w0, r5f104begna#w0, r5f104bfgna#w0, r5f104bggna#w0 32-pin plastic lqfp (7 7, 0.8 mm pitch) a r5f104baafp#v0, r5f104bcafp#v0, r5f104bdafp#v0, r5f104beafp#v0, r5f104bfafp#v0, r5f104bgafp#v0 r5f104baafp#x0, r5f104bcafp#x0, r5f104bdafp#x0, r5f104beafp#x0, r5f104bfafp#x0, r5f104bgafp#x0 d r5f104badfp#v0, r5f104bcdfp#v0, r5f104bddfp#v0, r5f104bedfp#v0, r5f104bfdfp#v0, r5f104bgdfp#v0 r5f104badfp#x0, r5f104bcdfp#x0, r5f104bddfp#x0, r5f104bedfp#x0, r5f104bfdfp#x0, r5f104bgdfp#x0 g r5f104bagfp#v0, r5f104bcgfp#v0, r5f104bdgfp#v0, r5f104begfp#v0, r5f104bfgfp#v0, r5f104bggfp#v0 r5f104bagfp#x0, r5f104bcgfp#x0, r5f104bdgfp#x0, r5f104begfp#x0, r5f104bfgfp#x0, r5f104bggfp#x0 36 pins 36-pin plastic wflga (4 4 mm, 0.5 mm pitch) a r5f104caala#u0, r5f104ccala#u0, r5f104cdala#u0, r5f104ceala#u0, r5f104cfala#u0, r5f104cgala#u0 r5f104caala#w0, r5f104ccala#w0, r5f104cdala#w0, r5f104ceala#w0, r5f104cfala#w0, r5f104cgala#w0 g r5f104cagla#u0, r5f104ccgla#u0, r5f104cdgla#u0, r5f104cegla#u0, r5f104cfgla#u0, r5f104cggla#u0 r5f104cagla#w0, r5f104ccgla#w0, r5f104cdgla#w0, r5f104cegla#w0, r5f104cfgla#w0, r5f104cggla#w0
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 5 of 208 aug 12, 2016 note for the fields of application, refer to figure 1 - 1 part number, memory size, and package of rl78/g14 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website. (2/5) pin count package fields of application note ordering part number 40 pins 40-pin plastic hwqfn (6 6 mm, 0.5 mm pitch) a r5f104eaana#u0, r5f104ecana#u0, r5f104edana#u0, r5f104eeana#u0, r5f104efana#u0, r5f104egana#u0, r5f104ehana#u0 r5f104eaana#w0, r5f104ecana#w0, r5f104edana#w0, r5f104eeana#w0, r5f104efana#w0, r5f104egana#w0, r5f104ehana#w0 d r5f104eadna#u0, r5f104ecdna#u0, r5f104eddna#u0, r5f104eedna#u0, r5f104efdna#u0, r5f104egdna#u0, r5f104ehdna#u0 r5f104eadna#w0, r5f104ecdna#w0, r5f104eddna#w0, r5f104eedna#w0, r5f104efdna#w0, r5f104egdna#w0, r5f104ehdna#w0 g r5f104eagna#u0, r5f104ecgna#u0, r5f104edgna#u0, r5f104eegna#u0, r5f104efgna#u0, r5f104eggna#u0, r5f104ehgna#u0 r5f104eagna#w0, r5f104ecgna#w0, r5f104edgna#w0, r5f104eegna#w0, r5f104efgna#w0, r5f104eggna#w0, r5f104ehgna#w0 44 pins 44-pin plastic lqfp (10 10, 0.8 mm pitch) a r5f104faafp#v0, r5f104fcafp#v0, r5f104fdafp#v0, r5f104feafp#v0, r5f104ffafp#v0, r5f104fgafp#v0, r5f104fhafp#v0, r5f104fjafp#v0 r5f104faafp#x0, r5f104fcafp#x0, r5f104fdafp#x0, r5f104feafp#x0, r5f104ffafp#x0, r5f104fgafp#x0, r5f104fhafp#x0, r5f104fjafp#x0 d r5f104fadfp#v0, r5f104fcdfp#v0, r5f104fddfp#v0, r5f104fedfp#v0, r5f104ffdfp#v0, r5f104fgdfp#v0, r5f104fhdfp#v0, r5f104fjdfp#v0 r5f104fadfp#x0, r5f104fcdfp#x0, r5f104fddfp#x0, r5f104fedfp#x0, r5f104ffdfp#x0, r5f104fgdfp#x0, r5f104fhdfp#x0, r5f104fjdfp#x0 g r5f104fagfp#v0, r5f104fcgfp#v0, r5f104fdgfp#v0, r5f104fegfp#v0, r5f104ffgfp#v0, r5f104fggfp#v0, r5f104fhgfp#v0, r5f104fjgfp#v0 r5f104fagfp#x0, r5f104fcgfp#x0, r5f104fdgfp#x0, r5f104fegfp#x0, r5f104ffgfp#x0, r5f104fggfp#x0, r5f104fhgfp#x0, r5f104fjgfp#x0
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 6 of 208 aug 12, 2016 note for the fields of application, refer to figure 1 - 1 part number, memory size, and package of rl78/g14 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website. (3/5) pin count package fields of application note ordering part number 48 pins 48-pin plastic lfqfp (7 7 mm, 0.5 mm pitch) a r5f104gaafb#v0, r5f104gcafb#v0, r5f104gdafb#v0, r5f104geafb#v0, r5f104gfafb#v0, r5f104ggafb#v0, r5f104ghafb#v0, r5f104gjafb#v0 r5f104gaafb#x0, r5f104gcafb#x0, r5f104gdafb#x0, r5f104geafb#x0, r5f104gfafb#x0, r5f104ggafb#x0, r5f104ghafb#x0, r5f104gjafb#x0 r5f104gkafb#30, r5f104glafb#30 r5f104gkafb#50, r5f104glafb#50 d r5f104gadfb#v0, r5f104gcdfb#v0, r5f104gddfb#v0, r5f104gedfb#v0, r5f104gfdfb#v0, r5f104ggdfb#v0, r5f104ghdfb#v0, r5f104gjdfb#v0 r5f104gadfb#x0, r5f104gcdfb#x0, r5f104gddfb#x0, r5f104gedfb#x0, r5f104gfdfb#x0, r5f104ggdfb#x0, r5f104ghdfb#x0, r5f104gjdfb#x0 g r5f104gagfb#v0, r5f104gcgfb#v0, r5f104gdgfb#v0, r5f104gegfb#v0, r5f104gfgfb#v0, r5f104gggfb#v0, r5f104ghgfb#v0, r5f104gjgfb#v0 r5f104gagfb#x0, r5f104gcgfb#x0, r5f104gdgfb#x0, r5f104gegfb#x0, r5f104gfgfb#x0, r5f104gggfb#x0, r5f104ghgfb#x0, r5f104gjgfb#x0 r5f104gkgfb#30, r5f104glgfb#30 r5f104gkgfb#50, r5f104glgfb#50 48-pin plastic hwqfn (7 7 mm, 0.5 mm pitch) a r5f104gaana#u0, r5f104gcana#u0, r5f104gdana#u0, r5f104geana#u0, r5f104gfana#u0, r5f104ggana#u0, r5f104ghana#u0, r5f104gjana#u0 r5f104gaana#w0, r5f104gcana#w0, r5f104gdana#w0, r5f104geana#w0, r5f104gfana#w0, r5f104ggana#w0, r5f104ghana#w0, r5f104gjana#w0 r5f104gkana#u0, r5f104glana#u0 r5f104gkana#w0, r5f104glana#w0 d r5f104gadna#u0, r5f104gcdna#u0, r5f104gddna#u0, r5f104gedna#u0, r5f104gfdna#u0, r5f104ggdna#u0, r5f104ghdna#u0, r5f104gjdna#u0 r5f104gadna#w0, r5f104gcdna#w0, r5f104gddna#w0, r5f104gedna#w0, r5f104gfdna#w0, r5f104ggdna#w0, r5f104ghdna#w0, r5f104gjdna#w0 g r5f104gagna#u0, r5f104gcgna#u0, r5f104gdgna#u0, r5f104gegna#u0, r5f104gfgna#u0, r5f104gggna#u0, r5f104ghgna#u0, r5f104gjgna#u0 r5f104gagna#w0, r5f104gcgna#w0, r5f104gdgna#w0, r5f104gegna#w0, r5f104gfgna#w0, r5f104gggna#w0, r5f104ghgna#w0, r5f104gjgna#w0 r5f104gkgna#u0, r5f104glgna#u0 r5f104gkgna#w0, r5f104glgna#w0 52 pins 52-pin plastic lqfp (10 10 mm, 0.65 mm pitch) a r5f104jcafa#v0, r5f104jdafa#v0, r5f104jeafa#v0, r5f104jfafa#v0, R5F104JGAfa#v0, r5f104jhafa#v0, r5f104jjafa#v0 r5f104jcafa#x0, r5f104jdafa#x0, r5f104jeafa#x0, r5f104jfafa#x0, R5F104JGAfa#x0, r5f104jhafa#x0, r5f104jjafa#x0 d r5f104jcdfa#v0, r5f104jddfa#v0, r5 f104jedfa#v0, r5f104jfdfa#v0, r5f104jgdfa#v0, r5f104jhdfa#v0, r5f104jjdfa#v0 r5f104jcdfa#x0, r5f104jddfa#x0, r5 f104jedfa#x0, r5f104jfdfa#x0, r5f104jgdfa#x0, r5f104jhdfa#x0, r5f104jjdfa#x0 g r5f104jcgfa#v0, r5f104jdgfa#v0, r5f104jegfa#v0, r5f104jfgfa#v0, r5f104jggfa#v0, r5f104jhgfa#v0, r5f104jjgfa#v0 r5f104jcgfa#x0, r5f104jdgfa#x0, r5f104jegfa#x0, r5f104jfgfa#x0, r5f104jggfa#x0, r5f104jhgfa#x0, r5f104jjgfa#x0
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 7 of 208 aug 12, 2016 note for the fields of application, refer to figure 1 - 1 part number, memory size, and package of rl78/g14 . caution the ordering part numbers represent the numbers at the time of publication. for the latest ordering part numbers, refer to the target product page of the renesas electronics website. (4/5) pin count package fields of application note ordering part number 64 pins 64-pin plastic lqfp (12 12 mm, 0.65 mm pitch) a r5f104lcafa#v0, r5f104ldafa#v0, r5f104leafa#v0, r5f104lfafa#v0, r5f104lgafa#v0, r5f104lhafa#v0, r5f104ljafa#v0 r5f104lcafa#x0, r5f104ldafa#x0, r5f104leafa#x0, r5f104lfafa#x0, r5f104lgafa#x0, r5f104lhafa#x0, r5f104ljafa#x0 r5f104lkafa#30, r5f104llafa#30 r5f104lkafa#50, r5f104llafa#50 d r5f104lcdfa#v0, r5f104lddfa#v0, r5f104ledfa#v0, r5f104lfdfa#v0, r5f104lgdfa#v0, r5f104lhdfa#v0, r5f104ljdfa#v0 r5f104lcdfa#x0, r5f104lddfa#x0, r5f104ledfa#x0, r5f104lfdfa#x0, r5f104lgdfa#x0, r5f104lhdfa#x0, r5f104ljdfa#x0 g r5f104lcgfa#v0, r5f104ldgfa#v0, r5f104legfa#v0, r5f104lfgfa#v0, r5f104lggfa#v0, r5f104lhgfa#v0, r5f104ljgfa#v0 r5f104lcgfa#x0, r5f104ldgfa#x0, r5f104legfa#x0, r5f104lfgfa#x0, r5f104lggfa#x0, r5f104lhgfa#x0, r5f104ljgfa#x0 r5f104lkgfa#30, r5f104llgfa#30 r5f104lkgfa#50, r5f104llgfa#50 64-pin plastic lfqfp (10 10 mm, 0.5 mm pitch) a r5f104lcafb#v0, r5f104ldafb#v0, r5f104leafb#v0, r5f104lfafb#v0, r5f104lgafb#v0, r5f104lhafb#v0, r5f104ljafb#v0 r5f104lcafb#x0, r5f104ldafb#x0, r5f104leafb#x0, r5f104lfafb#x0, r5f104lgafb#x0, r5f104lhafb#x0, r5f104ljafb#x0 r5f104lkafb#30, r5f104llafb#30 r5f104lkafb#50, r5f104llafb#50 d r5f104lcdfb#v0, r5f104lddfb#v0, r5f104ledfb#v0, r5f104lfdfb#v0, r5f104lgdfb#v0, r5f104lhdfb#v0, r5f104ljdfb#v0 r5f104lcdfb#x0, r5f104lddfb#x0, r5f104ledfb#x0, r5f104lfdfb#x0, r5f104lgdfb#x0, r5f104lhdfb#x0, r5f104ljdfb#x0 g r5f104lcgfb#v0, r5f104ldgfb#v0, r5f104legfb#v0, r5f104lfgfb#v0, r5f104lggfb#v0, r5f104lhgfb#v0, r5f104ljgfb#v0 r5f104lcgfb#x0, r5f104ldgfb#x0, r5f104legfb#x0, r5f104lfgfb#x0, r5f104lggfb#x0, r5f104lhgfb#x0, r5f104ljgfb#x0 r5f104lkgfb#30, r5f104llgfb#30 r5f104lkgfb#50, r5f104llgfb#50 64-pin plastic flga (5 5 mm, 0.5 mm pitch) a r5f104lcala#u0, r5f104ldala#u0, r5f104leala#u0, r5f104lfala#u0, r5f104lgala#u0, r5f104lhala#u0, r5f104ljala#u0 r5f104lcala#w0, r5f104ldala#w0, r5f104leala#w0, r5f104lfala#w0, r5f104lgala#w0, r5f104lhala#w0, r5f104ljala#w0 r5f104lkala#u0, r5f104llala#u0 r5f104lkala#w0, r5f104llala#w0 g r5f104lcgla#u0, r5f104ldgla#u0, r5f104legla#u0, r5f104lfgla#u0, r5f104lggla#u0, r5f104lhgla#u0, r5f104ljgla#u0, r5f104lkgla#u0, r5f104llgla#u0 r5f104lcgla#w0, r5f104ldgla#w0, r5f104legla#w0, r5f104lfgla#w0, r5f104lggla#w0, r5f104lhgla#w0, r5f104ljgla#w0, r5f104lkgla#w0, r5f104llgla#w0 64-pin plastic lqfp (14 14 mm, 0.8 mm pitch) a r5f104lcafp#v0, r5f104ldafp#v0, r5f104leafp#v0, r5f104lfafp#v0, r5f104lgafp#v0, r5f104lhafp#v0, r5f104ljafp#v0 r5f104lcafp#x0, r5f104ldafp#x0, r5f104leafp#x0, r5f104lfafp#x0, r5f104lgafp#x0, r5f104lhafp#x0, r5f104ljafp#x0 d r5f104lcdfp#v0, r5f104lddfp#v0, r5f104ledfp#v0, r5f104lfdfp#v0, r5f104lgdfp#v0, r5f104lhdfp#v0, r5f104ljdfp#v0 r5f104lcdfp#x0, r5f104lddfp#x0, r5f104ledfp#x0, r5f104lfdfp#x0, r5f104lgdfp#x0, r5f104lhdfp#x0, r5f104ljdfp#x0 g r5f104lcgfp#v0, r5f104ldgfp#v0, r5f104legfp#v0, r5f104lfgfp#v0, r5f104lggfp#v0, r5f104lhgfp#v0, r5f104ljgfp#v0 r5f104lcgfp#x0, r5f104ldgfp#x0, r5f104legfp#x0, r5f104lfgfp#x0, r5f104lggfp#x0, r5f104lhgfp#x0, r5f104ljgfp#x0
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 8 of 208 aug 12, 2016 note for the fields of application, refer to figure 1 - 1 part number, memory size, and package of rl78/g14 . caution the ordering part numbers represent the numbers at the time of publication. for the latest orderi ng part numbers, refer to the target product page of the renesas electronics website. (5/5) pin count package fields of application note ordering part number 80 pins 80-pin plastic lfqfp (12 12 mm, 0.5 mm pitch) a r5f104mfafb#v0, r5f104mgafb#v0, r5f104mhafb#v0, r5f104mjafb#v0 r5f104mfafb#x0, r5f104mgafb#x0, r5f104mhafb#x0, r5f104mjafb#x0 r5f104mkafb#30, r5f104mlafb#30 r5f104mkafb#50, r5f104mlafb#50 d r5f104mfdfb#v0, r5f104mgdfb#v0, r5f104mhdfb#v0, r5f104mjdfb#v0 r5f104mfdfb#x0, r5f104mgdfb#x0, r5f104mhdfb#x0, r5f104mjdfb#x0 g r5f104mfgfb#v0, r5f104mggfb#v0, r5f104mhgfb#v0, r5f104mjgfb#v0 r5f104mfgfb#x0, r5f104mggfb#x0, r5f104mhgfb#x0, r5f104mjgfb#x0 r5f104mkgfb#30, r5f104mlgfb#30 r5f104mkgfb#x0, r5f104mlgfb#50 80-pin plastic lqfp (14 14 mm, 0.65 mm pitch) a r5f104mfafa#v0, r5f104mgafa#v0, r5f104mhafa#v0, r5f104mjafa#v0 r5f104mfafa#x0, r5f104mgafa#x0, r5f104mhafa#x0, r5f104mjafa#x0 r5f104mkafa#30, r5f104mlafa#30 r5f104mkafa#50, r5f104mlafa#50 d r5f104mfdfa#v0, r5f104mgdfa#v0, r5f104mhdfa#v0, r5f104mjdfa#v0 r5f104mfdfa#x0, r5f104mgdfa#x0, r5f104mhdfa#x0, r5f104mjdfa#x0 g r5f104mfgfa#v0, r5f104mggfa#v0, r5f104mhgfa#v0, r5f104mjgfa#v0 r5f104mfgfa#x0, r5f104mggfa#x0, r5f104mhgfa#x0, r5f104mjgfa#x0 r5f104mkgfa#30, r5f104mlgfa#30 r5f104mkgfa#50, r5f104mlgfa#50 100 pins 100-pin plastic lfqfp (14 14 mm, 0.5 mm pitch) a r5f104pfafb#v0, r5f104pgafb#v0, r5f104phafb#v0, r5f104pjafb#v0 r5f104pfafb#x0, r5f104pgafb#x0, r5f104phafb#x0, r5f104pjafb#x0 r5f104pkafb#30, r5f104plafb#30 r5f104pkafb#50, r5f104plafb#50 d r5f104pfdfb#v0, r5f104pgdfb#v0, r5f104phdfb#v0, r5f104pjdfb#v0 r5f104pfdfb#x0, r5f104pgdfb#x0, r5f104phdfb#x0, r5f104pjdfb#x0 g r5f104pfgfb#v0, r5f104pggfb#v0, r5f104phgfb#v0, r5f104pjgfb#v0 r5f104pfgfb#x0, r5f104pggfb#x0, r5f104phgfb#x0, r5f104pjgfb#x0 r5f104pkgfb#30, r5f104plgfb#30 r5f104pkgfb#50, r5f104plgfb#50 100-pin plastic lqfp (14 20 mm, 0.65 mm pitch) a r5f104pfafa#v0, r5f104pgafa#v0, r5f104phafa#v0, r5f104pjafa#v0 r5f104pfafa#x0, r5f104pgafa#x0, r5f104phafa#x0, r5f104pjafa#x0 r5f104pkafa#30, r5f104plafa#30 r5f104pkafa#50, r5f104plafa#50 d r5f104pfdfa#v0, r5f104pgdfa#v0, r5f104phdfa#v0, r5f104pjdfa#v0 r5f104pfdfa#x0, r5f104pgdfa#x0, r5f104phdfa#x0, r5f104pjdfa#x0 g r5f104pfgfa#v0, r5f104pggfa#v0, r5f104phgfa#v0, r5f104pjgfa#v0 r5f104pfgfa#x0, r5f104pggfa#x0, r5f104phgfa#x0, r5f104pjgfa#x0 r5f104pkgfa#30, r5f104plgfa#30 r5f104pkgfa#50, r5f104plgfa#50
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 9 of 208 aug 12, 2016 1.3 pin configuration (top view) 1.3.1 30-pin products ? 30-pin plastic lssop (7.62 mm (300), 0.65 mm pitch) note mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p21/ani1/av refm p22/ani2/ano0 note p23/ani3 p147/ani18/vcout1 note p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1 p12/so11/trdiob1/ivref1 note p13/txd2/so20/trdioa1/ivcmp1 note p14/rxd2/si20/sda20/trdiod0/(scla0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0 note /(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0 note /(txd0) p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/sck00/scl00/trjo0 p01/ani16/to00/rxd1/trgclkb/trjio0 p00/ani17/ti00/txd1/trgclka/(trjo0) p120/ani19/vcout0 note p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p60/scla0 p61/sdaa0 p31/ti03/to03/intp4/pclbuz0/ssi00 /(trjio0) p20/ani0/av refp rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 10 of 208 aug 12, 2016 1.3.2 32-pin products ? 32-pin plastic hwqfn (5 5 mm, 0.5 mm pitch) note mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). remark 3. it is recommended to connect an exposed die pad to v ss . p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/sck00/scl00/trjo0 p70 p31/ti03/to03/intp4/pclbuz0/(trjio0) p62/ssi00 p61/sdaa0 p60/scla0 exposed die pad 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 1 p147/ani18/vcout1 note p23/ani3/ano1 note p22/ani2/ano0 note p20/ani0/av refp p01/ani16/to00/rxd1/trgclkb/trjio0 p00/ani17/ti00/txd1/trgclka/(trjo0) 23456 78 24 23 22 21 20 19 18 17 p40/tool0 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd reset p17/ti02/to02/trdioa0/trdclk/ivcmp0 note /(txd0) p16/ti01/to01/intp5/trdioc0/ivref0 note /(rxd0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p14/rxd2/si20/sda20/trdiod0/(scla0) p13/txd2/so20/trdioa1/ivcmp1 note p12/so11/trdiob1/ivref1 note p11/si11/sda11/trdioc1 p10/sck11/scl11/trdiod1 p120/ani19/vcout0 note p21/ani1/av refm rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 11 of 208 aug 12, 2016 ? 32-pin plastic lqfp (7 7 mm, 0.8 mm pitch) note mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/sck00/scl00/trjo0 p70 p31/ti03/to03/intp4/pclbuz0/(trjio0) p62/ssi00 p61/sdaa0 p60/scla0 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 1 p147/ani18/vcout1 note p23/ani3/ano1 note p22/ani2/ano0 note p20/ani0/av refp p01/ani16/to00/rxd1/trgclkb/trjio0 p00/ani17/ti00/txd1/trgclka/(trjo0) 2345678 24 23 22 21 20 19 18 17 p40/tool0 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd reset p17/ti02/to02/trdioa0/trdclk/ivcmp0 note /(txd0) p16/ti01/to01/intp5/trdioc0/ivref0 note /(rxd0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p14/rxd2/si20/sda20/trdiod0/(scla0) p13/txd2/so20/trdioa1/ivcmp1 note p12/so11/trdiob1/ivref1 note p11/si11/sda11/trdioc1 p10/sck11/scl11/trdiod1 p120/ani19/vcout0 note p21/ani1/av refm rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 12 of 208 aug 12, 2016 1.3.3 36-pin products ? 36-pin plastic wflga (4 4 mm, 0.5 mm pitch) note mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). abcdef 6 p60/scla0 v dd p121/x1 p122/x2/exclk p137/intp0 p40/tool0 6 5 p62/ssi00 p61/sdaa0 v ss regc reset p120/ani19/ vcout0 note 5 4 p72/so21 p71/si21/ sda21 p14/rxd2/si20/ sda20/trdiod0/ (scla0) p31/ti03/to03/ intp4/pclbuz0/ (trjio0) p00/ti00/txd1/ trgclka/ (trjo0) p01/to00/ rxd1/trgclkb/ trjio0 4 3 p50/intp1/ si00/rxd0/ toolrxd/ sda00/trgioa/ (trjo0) p70/sck21/ scl21 p15/pclbuz1/ sck20/scl20/ trdiob0/ (sdaa0) p22/ani2/ ano0 note p20/ani0/ av refp p21/ani1/ av refm 3 2 p30/intp3/ sck00/scl00/ trjo0 p16/ti01/to01/ intp5/trdioc0/ ivref0 note / (rxd0) p12/so11/ trdiob1/ ivref1 note p11/si11/ sda11/ trdioc1 p24/ani4 p23/ani3/ ano1 note 2 1 p51/intp2/ so00/txd0/ tooltxd/ trgiob p17/ti02/to02/ trdioa0/ trdclk/ ivcmp0 note / (txd0) p13/txd2/ so20/trdioa1/ ivcmp1 note p10/sck11/ scl11/ trdiod1 p147/ani18/ vcout1 note p25/ani5 1 abcdef top view bottom view 6 5 4 3 2 1 index mark abcdef fedcba rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 13 of 208 aug 12, 2016 1.3.4 40-pin products ? 40-pin plastic hwqfn (6 6 mm, 0.5 mm pitch) note mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). remark 3. it is recommended to connect an exposed die pad to v ss . 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 exposed die pad p26/ani6 p25/ani5 p24/ani4 p23/ani3/ano1 note p22/ani2/ano0 note p21/ani1/av refm p20/ani0/av refp p01/to00/rxd1/trgclkb/trjio0 p00/ti00/txd1/trgclka/(trjo0) p120/ani19/vcout0 note p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/rtc1hz/sck00/scl00/trjo0 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p31/ti03/to03/intp4/pclbuz0/(trjio0) p62/ssi00 p61/sdaa0 p60/scla0 12345678910 30 29 28 27 26 25 24 23 22 21 v dd v ss regc p121/x1 p137/intp0 p123/xt1 p124/xt2/exclks reset p40/tool0 p51/intp2/so00/txd0/tooltxd/trgiob p17/ti02/to02/trdioa0/trdclk/ivcmp0 note /(txd0) p16/ti01/to01/intp5/trdioc0/ivref0 note /(rxd0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p14/rxd2/si20/sda20/trdiod0/(scla0) p13/txd2/so20/trdioa1/ivcmp1 note p12/so11/trdiob1/ivref1 note p11/si11/sda11/trdioc1 p10/sck11/scl11/trdiod1 p147/ani18/vcout1 note p122/x2/exclk rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 14 of 208 aug 12, 2016 1.3.5 44-pin products ? 44-pin plastic lqfp (10 10 mm, 0.8 mm pitch) note mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3/ano1 note p22/ani2/ano0 note p21/ani1/av refm p20/ani0/av refp p01/to00/rxd1/trgclkb/trjio0 p00/ti00/txd1/trgclka/(trjo0) p120/ani19/vcout0 note p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/rtc1hz/sck00/scl00/trjo0 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p31/ti03/to03/intp4/pclbuz0/(trjio0) p63 p62/ssi00 p61/sdaa0 p60/scla0 33 32 31 30 29 28 27 26 25 24 1234567891011 23 p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p17/ti02/to02/trdioa0/trdclk/ivcmp0 note /(txd0) p16/ti01/to01/intp5/trdioc0/ivref0 note /(rxd0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p14/rxd2/si20/sda20/trdiod0/(scla0) p13/txd2/so20/trdioa1/ivcmp1 note p12/so11/trdiob1/ivref1 note p11/si11/sda11/trdioc1 p10/sck11/scl11/trdiod1 p146 p147/ani18/vcout1 note p51/intp2/so00/txd0/tooltxd/trgiob rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 15 of 208 aug 12, 2016 1.3.6 48-pin products ? 48-pin plastic lfqfp (7 7 mm, 0.5 mm pitch) note 1. mounted on the 96 kb or more code flash memory products. note 2. mounted on the 384 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). p147/ani18/vcout1 note 1 p146 p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note 2 p12/so11/trdiob1/ivref1 note 1 /(txd0_1) note 2 p13/txd2/so20/trdioa1/ivcmp1 note 1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0 note 1 /(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0 note 1 /(txd0) p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0 p120/ani19/vcout0 note 1 p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 p30/intp3/rtc1hz/sck00/scl00/trjo0 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3/so01 p74/kr4/intp8/si01/sda01 p75/kr5/intp9/sck01/scl01 p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p63 p62/ssi00 p61/sdaa0 p60/scla0 p140/pclbuz0/intp6 p00/ti00/txd1/trgclka/(trjo0) p01/to00/rxd1/trgclkb/trjio0 p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/ano0 note 1 p23/ani3/ano1 note 1 p24/ani4 p25/ani5 p26/ani6 p27/ani7 rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 16 of 208 aug 12, 2016 ? 48-pin plastic hwqfn (7 7 mm, 0.5 mm pitch) note 1. mounted on the 96 kb or more code flash memory products. note 2. mounted on the 384 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). remark 3. it is recommended to connect an exposed die pad to v ss . p147/ani18/vcout1 note 1 p146 p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note 2 p12/so11/trdiob1/ivref1 note 1 /(txd0_1) note 2 p13/txd2/so20/trdioa1/ivcmp1 note 1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0 note 1 /(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0 note 1 /(txd0) p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0 p120/ani19/vcout0 note 1 p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 p30/intp3/rtc1hz/sck00/scl00/trjo0 p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3/so01 p74/kr4/intp8/si01/sda01 p75/kr5/intp9/sck01/scl01 p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p63 p62/ssi00 p61/sdaa0 p60/scla0 p140/pclbuz0/intp6 p00/ti00/txd1/trgclka/(trjo0) p01/to00/rxd1/trgclkb/trjio0 p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/ano0 note 1 p23/ani3/ano1 note 1 p24/ani4 p25/ani5 p26/ani6 p27/ani7 exposed die pad rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 17 of 208 aug 12, 2016 1.3.7 52-pin products ? 52-pin plastic lqfp (10 10 mm, 0.65 mm pitch) note 1. mounted on the 96 kb or more code flash memory products. caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3/so01 p74/kr4/intp8/si01/sda01 p75/kr5/intp9/sck01/scl01 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p63 p62/ssi00 p61/sdaa0 p60/scla0 26 25 24 23 22 21 20 19 18 17 16 15 14 40 41 42 43 44 45 46 47 48 49 50 51 52 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3/ano1 note 1 p22/ani2/ano0 note 1 p21/ani1/av refm p20/ani0/av refp p130 p03/ani16/rxd1 p02/ani17/txd1 p01/to00/trgclkb/trjio0 p00/ti00/trgclka/(trjo0) p140/pclbuz0/intp6 reset p41/(trjio0) p40/tool0 p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p147/ani18/vcout1 note 1 p146 p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note 2 p12/so11/trdiob1/ivref1 note 1 /(txd0_1) note 2 p13/txd2/so20/trdioa1/ivcmp1 note 1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/pclbuz1/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0 note 1 /(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0 note 1 /(txd0) p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/rtc1hz/sck00/scl00/trjo0 123456 78910 13 12 11 39 38 37 36 35 34 33 32 31 30 27 28 29 p120/ani19/vcout0 note 1 rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 18 of 208 aug 12, 2016 1.3.8 64-pin products ? 64-pin plastic lqfp (14 14 mm, 0.8 mm pitch) ? 64-pin plastic lqfp (12 12 mm, 0.65 mm pitch) ? 64-pin plastic lfqfp (10 10 mm, 0.5 mm pitch) note 1. mounted on the 96 kb or more code flash memory products. note 2. mounted on the 384 kb or more code flash memory products. caution 1. make ev ss0 pin the same potential as v ss pin. caution 2. make v dd pin the potential that is higher than ev dd0 pin. caution 3. connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. when using the microcontroller for an application where t he noise generated inside the micr ocontroller must be reduced, it is recommended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. remark 3. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3/ano1 note 1 p22/ani2/ano0 note 1 p21/ani1/av refm p20/ani0/av refp p130 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00/trgclkb/trjio0 p00/ti00/trgclka/(trjo0) p141/pclbuz1/intp7 p140/pclbuz0/intp6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p147/ani18/vcout1 note 1 p146 p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note 2 p12/so11/trdiob1/ivref1 note 1 /(intp5)/(txd0_1) note 2 p13/txd2/so20/trdioa1/ivcmp1 note 1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0 note 1 /(si00)/(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0 note 1 /(so00)/(txd0) p55/(pclbuz1)/(sck00)/(intp4) p54/(intp3) p53/(intp2) p52/(intp1) p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) p30/intp3/rtc1hz/sck00/scl00/trjo0 p05/(intp10) p06/(intp11)/(trjio0) p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3/so01 p74/kr4/intp8/si01/sda01 p75/kr5/intp9/sck01/scl01 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p63 p62/ssi00 p61/sdaa0 p60/scla0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10111213141516 p120/ani19/vcout0 note 1 p43/(intp9) p42/(intp8) p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 19 of 208 aug 12, 2016 ? 64-pin plastic flga (5 5 mm, 0.5 mm pitch) note 1. mounted on the 96 kb or more code flash memory products. note 2. mounted on the 384 kb or more code flash memory products. caution 1. make ev ss0 pin the same potential as vss pin. caution 2. make v dd pin the potential that is higher than ev dd0 pin. caution 3. connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. when using the microcontroller for an application where t he noise generated inside the micr ocontroller must be reduced, it is recommended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. remark 3. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). abcdefgh 8 ev dd0 ev ss0 p121/x1 p122/x2/ exclk p137/intp0 p123/xt1 p124/xt2/ exclks p120/ani19/ vcout0 note 1 8 7 p60/scla0 v dd v ss regc reset p01/to00/ trgclkb/ trjio0 p00/ti00/ trgclka/ (trjo0) p140/ pclbuz0/ intp6 7 6 p61/sdaa0 p62/ssi00 p63 p40/tool0 p41/(trjio0) p43/(intp9) p02/ani17/ so10/txd1 p141/ pclbuz1/ intp7 6 5 p77/kr7/ intp11/(txd2) p31/ti03/ to03/intp4/ (pclbuz0)/ (trjio0) p53/(intp2) p42/( intp8) p03/ani16/ si10/rxd1/ sda10 p04/sck10/ scl10 p130 p20/ani0/ av refp 5 4 p75/kr5/ intp9/ sck01/ scl01 p76/kr6/ intp10/ (rxd2) p52/(intp1) p54/(intp3) p16/ti01/ to01/intp5/ trdioc0/ ivref0 note 1 / (si00)/(rxd0) p21/ani1/ av refm p22/ani2/ ano0 note 1 p23/ani3/ ano1 note 1 4 3 p70/kr0/ sck21/ scl21 p73/kr3/ so01 p74/kr4/ intp8/si01/ sda01 p17/ti02/to02/ trdioa0/ trdclk/ ivcmp0 note 1 / (so00)/(txd0) p15/sck20/ scl20/ trdiob0/ (sdaa0) p12/so11/ trdiob1/ ivref1 note 1 / (intp5)/ (txd0_1) note 2 p24/ani4 p26/ani6 3 2 p30/intp3/ rtc1hz/ sck00/ scl00/trjo0 p72/kr2/ so21 p71/kr1/ si21/sda21 p06/(intp11)/ (trjio0) p14/rxd2/ si20/sda20/ trdiod0/ (scla0) p11/si11/ sda11/ trdioc1/ (rxd0_1) note 2 p25/ani5 p27/ani7 2 1 p05/(intp10) p50/intp1/ si00/rxd0/ toolrxd/ sda00/ trgioa/ (trjo0) p51/intp2/ so00/txd0/ tooltxd/ trgiob p55/ (pclbuz1)/ (sck00)/ (intp4) p13/txd2/ so20/ trdioa1/ ivcmp1 note 1 p10/sck11/ scl11/ trdiod1 p146 p147/ani18/ vcout1 note 1 1 abcdefgh 1 hgfedcba 2 3 4 5 6 7 8 a b cde f gh top view bottom view index mark rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 20 of 208 aug 12, 2016 1.3.9 80-pin products ? 80-pin plastic lqfp (14 14 mm, 0.65 mm pitch) ? 80-pin plastic lfqfp (12 12 mm, 0.5 mm pitch) note mounted on the 384 kb or more code flash memory products. caution 1. make ev ss0 pin the same potential as v ss pin. caution 2. make v dd pin the potential that is higher than ev dd0 pin. caution 3. connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. when using the microcontroller for an application where t he noise generated inside the micr ocontroller must be reduced, it is recommended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. remark 3. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). p152/ani10 p151/ani9 p150/ani8 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3/ano1 p22/ani2/ano0 p21/ani1/av refm p20/ani0/av refp p130 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00/trgclkb/trjio0 p00/ti00/trgclka/(trjo0) p144/so30/txd3 p143/si30/rxd3/sda30 p142/sck30/scl30 p30/intp3/rtc1hz/sck00/scl00/trjo0 p05 p06/(trjio0) p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p74/kr4/intp8 p75/kr5/intp9 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p67/ti13/to13 p66/ti12/to12 p65/ti11/to11 p64/ti10/to10 p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p63/sdaa1 p62/ssi00 /scla1 p61/sdaa0 p60/scla0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 1011121314151617181920 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p141/pclbuz1/intp7 p140/pclbuz0/intp6 p120/ani19/vcout0 p45/so01 p44/si01/sda01 p43/sck01/scl01/(intp9) p42/(intp8) p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 p153/ani11 p100/ani20/(intp10) p147/ani18/vcout1 p146 p111 p110/(intp11) p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note p12/so11/trdiob1/ivref1/(intp5)/(txd0_1) note p13/txd2/so20/trdioa1/ivcmp1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0/(si00)/(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0/(so00)/(txd0) p55/(pclbuz1)/(sck00)/(intp4) p54/sck31/scl31/(intp3) p53/si31/sda31/(intp2) p52/so31/(intp1) p51/intp2/so00/txd0/tooltxd/trgiob p50/intp1/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 21 of 208 aug 12, 2016 1.3.10 100-pin products ? 100-pin plastic lfqfp (14 14 mm, 0.5 mm pitch) note mounted on the 384 kb or more code flash memory products. caution 1. make ev ss0 , ev ss1 pins the same potential as v ss pin. caution 2. make v dd pin the potential that is higher than ev dd0 , ev dd1 pins (ev dd0 = ev dd1 ). caution 3. connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. when using the microcontroller for an application where t he noise generated inside the micr ocontroller must be reduced, it is recommended to supply separate powers to the v dd, ev dd0 and ev dd1 pins and connect the v ss, ev ss0 and ev ss1 pins to separate ground lines. remark 3. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). 1 2 3 4 5 6 7 8 9 1011121314151617181920 p142/sck30/scl30 p141/pclbuz1/intp7 p140/pclbuz0/intp6 p120/ani19/vcout0 p47/intp2 p46/intp1 p45/so01 p44/si01/sda01 p43/sck01/scl01 p42 p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss 21 22 23 24 25 ev ss0 v dd ev dd0 p60/scla0 p61/sdaa0 p81/(si10)/(rxd1)/(sda10) p80/(sck10)/(scl10) ev ss1 p05 p06/(trjio0) p70/kr0/sck21/scl21 p71/kr1/si21/sda21 p72/kr2/so21 p73/kr3 p74/kr4/intp8 p75/kr5/intp9 p76/kr6/intp10/(rxd2) p77/kr7/intp11/(txd2) p67/ti13/to13 p66/ti12/to12 p65/ti11/to11 p64/ti10/to10 p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p63/sdaa1 p62/ssi00 /scla1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 p100/ani20/(intp10) p147/ani18/vcout1 p146/(intp4) p111 p110/(intp11) p101 p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note p12/so11/trdiob1/ivref1/(intp5)/(txd0_1) note p13/txd2/so20/trdioa1/ivcmp1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0/(si00)/(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0/(so00)/(txd0) p57/(intp3) p56/(intp1) p55/(pclbuz1)/(sck00) p54/sck31/scl31 p53/si31/sda31 p150/ani8 p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3/ano1 p22/ani2/ano0 p21/ani1/av refm p20/ani0/av refp p130 p102 p04/sck10/scl10 p03/ani16/si10/rxd1/sda10 p02/ani17/so10/txd1 p01/to00/trgclkb/trjio0 p00/ti00/trgclka/(trjo0) p145 p144/so30/txd3 p143/si30/rxd3/sda30 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p151/ani9 81 p152/ani10 80 p153/ani11 79 p154/ani12 78 p155/ani13 77 p156/ani14 76 56 p52/so31 55 p51/so00/txd0/tooltxd/trgiob 54 p50/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) 53 ev dd1 52 p30/intp3/rtc1hz/sck00/scl00/trjo0 51 p87/(intp9) p86/(intp8) p85/(intp7) p84/(intp6) p83 p82/(so10)/(txd1) rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 22 of 208 aug 12, 2016 ? 100-pin plastic lqfp (14 20 mm, 0.65 mm pitch) note mounted on the 384 kb or more code flash memory products. caution 1. make ev ss0 , ev ss1 pins the same potential as v ss pin. caution 2. make v dd pin the potential that is higher than ev dd0 , ev dd1 pins (ev dd0 = ev dd1 ). caution 3. connect the regc pin to v ss pin via a capacitor (0.47 to 1 f). remark 1. for pin identification, see 1.4 pin identification . remark 2. when using the microcontroller for an application where t he noise generated inside the micr ocontroller must be reduced, it is recommended to supply separate powers to the v dd, ev dd0 and ev dd1 pins and connect the v ss, ev ss0 and ev ss1 pins to separate ground lines. remark 3. functions in parentheses in the above figure can be assigned via settings in the per ipheral i/o redirection register 0, 1 (pior0, 1). p146/(intp4) p111 p110/(intp11) p101 p10/sck11/scl11/trdiod1 p11/si11/sda11/trdioc1/(rxd0_1) note p12/so11/trdiob1/ivref1/(intp5)/(txd0_1) note p13/txd2/so20/trdioa1/ivcmp1 p14/rxd2/si20/sda20/trdiod0/(scla0) p15/sck20/scl20/trdiob0/(sdaa0) p16/ti01/to01/intp5/trdioc0/ivref0/(si00)/(rxd0) p17/ti02/to02/trdioa0/trdclk/ivcmp0/(so00)/(txd0) p57/(intp3) p56/(intp1) p55/(pclbuz1)/(sck00) p54/sck31/scl31 p53/si31/sda31 p52/so31 p51/so00/txd0/tooltxd/trgiob p50/si00/rxd0/toolrxd/sda00/trgioa/(trjo0) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p60/scla0 p61/sdaa0 p62/ssi00 /scla1 p63/sdaa1 p31/ti03/to03/intp4/(pclbuz0)/(trjio0) p64/ti10/to10 p65/ti11/to11 p66/ti12/to12 p67/ti13/to13 p77/kr7/intp11/(txd2) p76/kr6/intp10/(rxd2) p75/kr5/intp9 p74/kr4/intp8 p73/kr3 p72/kr2/so21 p71/kr1/si21/sda21 p70/kr0/sck21/scl21 p06/(trjio0) p05 ev ss1 p80/(sck10)/(scl10) p81/(si10)/(rxd1)/(sda10) p82/(so10)/(txd1) p83 p84/(intp6) p85/(intp7) p86/(intp8) p87/(intp9) p30/intp3/rtc1hz/sck00/scl00/trjo0 ev dd1 p140/pclbuz0/intp6 p141/pclbuz1/intp7 p142/sck30/scl30 p143/si30/rxd3/sda30 p144/so30/txd3 p145 p00/ti00/trgclka/(trjo0) p01/to00/trgclkb/trjio0 p02/ani17/so10/txd1 p03/ani16/si10/rxd1/sda10 p04/sck10/scl10 p102 p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/ano0 p23/ani3/ano1 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p153/ani11 p154/ani12 p155/ani13 p156/ani14 p100/ani20/(intp10) p147/ani18/vcout1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p120/ani19/vcout0 p47/intp2 p46/intp1 p45/so01 p44/si01/sda01 p43/sck01/scl01 p42 p41/(trjio0) p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 rl78/g14 (top view)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 23 of 208 aug 12, 2016 1.4 pin identification ani0 to ani14,: analog input ani16 to ani20 ano0, ano1: analog output av refm : a/d converter reference potential ( ? side) input av refp : a/d converter reference potential (+ side) input ev dd0 , ev dd1 : power supply for port ev ss0 , ev ss1 : ground for port exclk: external clock input (main system clock) exclks: external clock input (subsystem clock) intp0 to intp11: external interrupt input ivcmp0, ivcmp1: comparator input ivref0, ivref1: comparator reference input kr0 to kr7: key return p00 to p06: port 0 p10 to p17: port 1 p20 to p27: port 2 p30, p31: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p80 to p87: port 8 p100 to p102: port 10 p110, p111: port 11 p120 to p124: port 12 p130, p137: port 13 p140 to p147: port 14 p150 to p156: port 15 pclbuz0, pclbuz1: programmable clock output/buzzer output regc: regulator capacitance reset : reset rtc1hz: real-time clock correction clock (1 hz) output rxd0 to rxd3: receive data sck00, sck01, sck10,: serial clock input/output sck11, sck20, sck21, sck30, sck31 scla0, scla1,: serial clock input/output scl00, scl01, scl10, scl11,: serial clock output scl20, scl21, scl30, scl31 sdaa0, sdaa1, sda00,: serial data input/output sda01, sda10, sda11, sda20, sda21, sda30, sda31 si00, si01, si10, si11,: serial data input si20, si21, si30, si31 so00, so01, so10,: serial data output so11, so20, so21, so30, so31 ssi00 : serial interface chip select input ti00 to ti03,: timer input ti10 to ti13 to00 to to03,: timer output to10 to to13, trjo0 tool0: data input/output for tool toolrxd, tooltxd: data input/output for external device trdclk, trgclka,: timer external input clock trgclkb trdioa0, trdiob0,: timer input/output trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trgioa, trgiob, trjio0 txd0 to txd3: transmit data vcout0, vcout1: comparator output v dd : power supply v ss : ground x1, x2: crystal oscillat or (main system clock) xt1, xt2: crystal oscill ator (subsystem clock)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 24 of 208 aug 12, 2016 1.5 block diagram 1.5.1 30-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 4 ani0/p20 to ani3/p23 sck11/p10 so11/p12 si11/p11 scl11/p10 sda11/p11 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 intp5/p16 buzzer output clock output control rxd2/p14 txd2/p13 scl20/p15 sda20/p14 sck20/p15 so20/p13 si20/p14 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p31 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel csi11 iic00 iic11 to00/p01 rxd0/p50 (linsel) serial array unit1 (2ch) uart2 csi20 iic20 port 1 p10 to p17 8 port 2 p20 to p23 4 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p60, p61 2 port 4 p40 p120 port 12 p121, p122 p137 port 13 p147 port 14 a/d converter ani16/p01, ani17/p00 ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug x2/exclk/p122 x1/p121 reset 2 2 ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 2 code flash memory data flash memory pclbuz0/p31, pclbuz1/p15 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 25 of 208 aug 12, 2016 1.5.2 32-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 4 ani0/p20 to ani3/p23 sck11/p10 so11/p12 si11/p11 scl11/p10 sda11/p11 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 intp5/p16 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 sck20/p15 so20/p13 si20/p14 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel csi11 iic00 iic11 to00/p01 rxd0/p50 (linsel) serial array unit1 (2ch) uart2 csi20 iic20 port 1 p10 to p17 8 port 2 p20 to p23 4 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p60 to p62 3 p120 port 12 p121, p122 p137 port 13 p147 port 14 a/d converter ani16/p01, ani17/p00 ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug x2/exclk/p122 x1/p121 reset 2 2 ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 2 ano1/p23 port 4 p40 port 7 p70 code flash memory data flash memory buzzer output clock output control pclbuz0/p31, pclbuz1/p15 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 26 of 208 aug 12, 2016 1.5.3 36-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 6 ani0/p20 to ani5/p25 sck11/p10 so11/p12 si11/p11 scl11/p10 sda11/p11 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 intp5/p16 rxd2/p14 txd2/p13 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel csi11 iic00 iic11 to00/p01 rxd0/p50 (linsel) serial array unit1 (2ch) uart2 port 1 p10 to p17 8 port 2 p20 to p25 6 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121, p122 p137 port 13 p147 port 14 a/d converter ani18/p147, ani19/p120 2 av refp /p20 av refm /p21 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug x2/exclk/p122 x1/p121 reset 2 2 ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 2 ano1/p23 port 4 p40 port 7 p70 to p72 p60 to p62 3 3 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 sck21/p70 so21/p72 si21/p71 csi21 scl21/p70 sda21/p71 iic21 code flash memory data flash memory buzzer output pclbuz0/p31, pclbuz1/p15 clock output control 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 27 of 208 aug 12, 2016 1.5.4 40-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) sck11/p10 so11/p12 si11/p11 scl11/p10 sda11/p11 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 intp5/p16 rxd2/p14 txd2/p13 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel csi11 iic00 iic11 to00/p01 rxd0/p50 (linsel) serial array unit1 (2ch) uart2 port 1 p10 to p17 8 port 2 p20 to p26 7 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121 to p124 p137 port 13 p147 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug 2 2 ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 4 ano1/p23 port 4 p40 port 7 p70 to p73 p60 to p62 3 4 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 sck21/p70 so21/p72 si21/p71 csi21 scl21/p70 sda21/p71 iic21 7 ani0/p20 to ani6/p26 a/d converter ani18/p147, ani19/p120 2 av refp /p20 av refm /p21 key return kr0/p70 to kr3/p73 4 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 code flash memory data flash memory buzzer output pclbuz0/p31, pclbuz1/p15 clock output control 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 28 of 208 aug 12, 2016 1.5.5 44-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 scl00/p30 sda00/p50 ti02/to02/p17 ti03/to03/p31 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) sck11/p10 so11/p12 si11/p11 scl11/p10 sda11/p11 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 intp5/p16 rxd2/p14 txd2/p13 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel csi11 iic00 iic11 to00/p01 rxd0/p50 (linsel) serial array unit1 (2ch) uart2 port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121 to p124 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug 2 2 ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 4 ano1/p23 port 4 p40, p41 port 7 p70 to p73 p60 to p63 4 4 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 sck21/p70 so21/p72 si21/p71 csi21 scl21/p70 sda21/p71 iic21 8 ani0/p20 to ani7/p27 a/d converter ani18/p147, ani19/p120 2 av refp /p20 av refm /p21 key return kr0/p70 to kr3/p73 4 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 2 p146, p147 2 code flash memory data flash memory buzzer output pclbuz0/p31, pclbuz1/p15 clock output control 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 29 of 208 aug 12, 2016 1.5.6 48-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p01 txd1/p00 ti02/to02/p17 ti03/to03/p31 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel to00/p01 rxd0/p50 (linsel) port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00, p01 2 port 5 p50, p51 2 port 6 p120 port 12 p121 to p124 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 4 ano1/p23 port 4 p40, p41 port 7 p70 to p75 p60 to p63 4 6 8 ani0/p20 to ani7/p27 a/d converter ani18/p147, ani19/p120 2 av refp /p20 av refm /p21 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 2 p140, p146, p147 3 scl00/p30 sda00/p50 iic00 scl01/p75 sda01/p74 iic01 scl11/p10 sda11/p11 iic11 sck11/p10 so11/p12 si11/p11 csi11 sck01/p75 so01/p73 si01/p74 csi01 rxd2/p14 txd2/p13 serial array unit1 (2ch) uart2 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 sck21/p70 so21/p72 si21/p71 csi21 scl21/p70 sda21/p71 iic21 p130 key return kr0/p70 to kr5/p75 6 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 2 2 intp5/p16 intp6/p140 2 intp8/p74, intp9/p75 code flash memory data flash memory buzzer output pclbuz0/p140, pclbuz1/p15 clock output control 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 30 of 208 aug 12, 2016 1.5.7 52-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p03 txd1/p02 ti02/to02/p17 ti03/to03/p31 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 v ss toolrxd/p50, tooltxd/p51 v dd sdaa0/p61 scla0/p60 serial interface iica0 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel to00/p01 rxd0/p50 (linsel) port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00 to p03 4 port 5 p50, p51 2 port 6 p120 port 12 p121 to p124 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 4 ano1/p23 port 4 p40, p41 port 7 p70 to p77 p60 to p63 4 8 8 ani0/p20 to ani7/p27 a/d converter ani16/p03, ani17/p02, ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 2 p140, p146, p147 3 scl00/p30 sda00/p50 iic00 scl01/p75 sda01/p74 iic01 scl11/p10 sda11/p11 iic11 sck11/p10 so11/p12 si11/p11 csi11 sck01/p75 so01/p73 si01/p74 csi01 rxd2/p14 txd2/p13 serial array unit1 (2ch) uart2 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 sck21/p70 so21/p72 si21/p71 csi21 scl21/p70 sda21/p71 iic21 p130 key return kr0/p70 to kr7/p77 8 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 2 2 intp5/p16 intp6/p140 4 intp8/p74 to intp11/p77 code flash memory data flash memory buzzer output pclbuz0/p140, pclbuz1/p15 clock output control 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 31 of 208 aug 12, 2016 1.5.8 64-pin products note mounted on the 96 kb or more code flash memory products. voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p03 txd1/p02 ti02/to02/p17 ti03/to03/p31 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 timer rj trjio0/p01 trjo0/p30 ssi00 /p62 ch0 timer array unit (4ch) ch1 ch2 ch3 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel to00/p01 rxd0/p50 (linsel) port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00 to p06 7 port 5 p50 to p55 6 port 6 p120 port 12 p121 to p124 p137 port 13 port 14 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug ano0/p22 d/a converter note comparator note (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 4 ano1/p23 port 4 p40 to p43 port 7 p70 to p77 p60 to p63 4 8 8 ani0/p20 to ani7/p27 a/d converter ani16/p03, ani17/p02, ani18/p147, ani19/p120 4 av refp /p20 av refm /p21 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 4 p140, p141, p146, p147 4 scl00/p30 sda00/p50 iic00 scl01/p75 sda01/p74 iic01 scl11/p10 sda11/p11 iic11 sck11/p10 so11/p12 si11/p11 csi11 sck01/p75 so01/p73 si01/p74 csi01 rxd2/p14 txd2/p13 serial array unit1 (2ch) uart2 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 sck21/p70 so21/p72 si21/p71 csi21 scl21/p70 sda21/p71 iic21 p130 key return kr0/p70 to kr7/p77 8 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 2 2 intp5/p16 intp6/p140, intp7/p141 4 intp8/p74 to intp11/p77 sck10/p04 so10/p02 si10/p03 csi10 scl10/p04 sda10/p03 iic10 sdaa0/p61 scla0/p60 serial interface iica0 v dd , ev dd0 v ss , ev ss0 toolrxd/p50, tooltxd/p51 2 code flash memory data flash memory buzzer output pclbuz0/p140, pclbuz1/p141 clock output control 2 bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 32 of 208 aug 12, 2016 1.5.9 80-pin products voltage regulator regc interrupt control ram system control high-speed on-chip oscillator rxd0/p50 txd0/p51 uart1 rxd1/p03 txd1/p02 ti02/to02/p17 ti03/to03/p31 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 ssi00 /p62 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel to00/p01 rxd0/p50 (linsel) port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00 to p06 7 port 5 p50 to p55 6 port 6 p120 port 12 p121 to p124 p137 port 13 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug ano0/p22 d/a converter comparator (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 4 ano1/p23 port 4 p40 to p45 p60 to p67 8 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 6 scl00/p30 sda00/p50 iic00 scl01/p43 sda01/p44 iic01 scl11/p10 sda11/p11 iic11 sck11/p10 so11/p12 si11/p11 csi11 sck01/p43 so01/p45 si01/p44 csi01 serial array unit1 (4ch) p130 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd0/p50 (linsel) 2 2 intp5/p16 intp6/p140, intp7/p141 4 intp8/p74 to intp11/p77 sck10/p04 so10/p02 si10/p03 csi10 scl10/p04 sda10/p03 iic10 v dd , ev dd0 v ss , ev ss0 toolrxd/p50, tooltxd/p51 2 rxd2/p14 txd2/p13 uart2 rxd3/p143 txd3/p144 uart3 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 scl21/p70 sda21/p71 iic21 sck21/p70 so21/p72 si21/p71 csi21 sck30/p142 so30/p144 si30/p143 csi30 sck31/p54 so31/p52 si31/p53 csi31 scl30/p142 sda30/p143 iic30 scl31/p54 sda31/p53 iic31 ch0 timer array unit0 (4ch) ch1 ch2 ch3 ch0 timer array unit1 (4ch) ch1 ch2 ch3 ti10/to10/p64 ti11/to11/p65 ti12/to12/p66 ti13/to13/p67 a/d converter av refp /p20 av refm /p21 8 ani0/p20 to ani7/p27 ani8/p150 to ani11/p153 4 ani16/p03, ani17/p02, ani18/p147, ani19/p120, ani20/p100 5 timer rj trjio0/p01 trjo0/p30 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 buzzer output pclbuz0/p140, pclbuz1/p141 clock output control 2 sdaa0/p61 scla0/p60 serial interface iica0 sdaa1/p63 scla1/p62 serial interface iica1 port 7 p70 to p77 8 port 10 p100 port 11 p110, p111 2 port 14 p140 to p144, p146, p147 7 port 15 p150 to p153 4 key return kr0/p70 to kr7/p77 8 code flash memory data flash memory bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 33 of 208 aug 12, 2016 1.5.10 100-pin products ram rxd0/p50 txd0/p51 uart1 rxd1/p03 txd1/p02 ti02/to02/p17 ti03/to03/p31 ti00/p00 csi00 sck00/p30 so00/p51 si00/p50 ti01/to01/p16 trdioa0/trdclk/p17 trdiob0/p15, trdioc0/p16, trdiod0/p14 4 trdioa1/p13 totrdiod1/p10 3 ssi00 /p62 timer rd (2ch) ch0 ch1 serial array unit0 (4ch) uart0 linsel to00/p01 rxd0/p50 (linsel) port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30, p31 2 port 0 p00 to p06 7 port 5 p50 to p57 8 port 6 port 4 p40 to p47 p60 to p67 8 8 scl00/p30 sda00/p50 iic00 scl01/p43 sda01/p44 iic01 scl11/p10 sda11/p11 iic11 sck11/p10 so11/p12 si11/p11 csi11 sck01/p43 so01/p45 si01/p44 csi01 serial array unit1 (4ch) sck10/p04 so10/p02 si10/p03 csi10 scl10/p04 sda10/p03 iic10 toolrxd/p50, tooltxd/p51 rxd2/p14 txd2/p13 uart2 rxd3/p143 txd3/p144 uart3 sck20/p15 so20/p13 si20/p14 csi20 scl20/p15 sda20/p14 iic20 scl21/p70 sda21/p71 iic21 sck21/p70 so21/p72 si21/p71 csi21 sck30/p142 so30/p144 si30/p143 csi30 sck31/p54 so31/p52 si31/p53 csi31 scl30/p142 sda30/p143 iic30 scl31/p54 sda31/p53 iic31 ch0 timer array unit0 (4ch) ch1 ch2 ch3 ch0 timer array unit1 (4ch) ch1 ch2 ch3 ti10/to10/p64 ti11/to11/p65 ti12/to12/p66 ti13/to13/p67 timer rj trjio0/p01 trjo0/p30 timer rg trgioa/p50, trgiob/p51 2 2 trgclka/p00, trgclkb/p01 buzzer output pclbuz0/p140, pclbuz1/p141 clock output control 2 sdaa0/p61 scla0/p60 serial interface iica0 sdaa1/p63 scla1/p62 serial interface iica1 v ss , ev ss0 , ev ss1 v dd , ev dd0 , ev dd1 voltage regulator regc interrupt control system control high-speed on-chip oscillator p120 port 12 p121 to p124 p137 port 13 power on reset/ voltage detector por/lvd control reset control tool0/p40 on-chip debug ano0/p22 d/a converter comparator (2ch) comparator0 ivcmp0/p17 ivref0/p16 vcout0/p120 comparator1 ivcmp1/p13 ivref1/p12 vcout1/p147 4 ano1/p23 x1/p121 reset x2/exclk/p122 xt1/p123 xt2/exclks/p124 p130 intp0/p137 intp3/p30, intp4/p31 intp1/p47, intp2/p46 rxd0/p50 (linsel) 2 2 intp5/p16 intp6/p140, intp7/p141 4 intp8/p74 to intp11/p77 2 port 10 p100 to p102 port 11 p110, p111 2 port 14 p140 to p147 8 port 15 p150 to p156 7 key return kr0/p70 to kr7/p77 8 3 port 7 p70 to p77 8 port 8 p80 to p87 8 code flash memory data flash memory bcd adjustment data transfer control event link controller window watchdog timer 12- bit interval timer real-time clock low-speed on-chip oscillator rtc1hz/p30 a/d converter av refp /p20 av refm /p21 8 ani0/p20 to ani7/p27 ani8/p150 to ani14/p156 7 ani16/p03, ani17/p02, ani18/p147, ani19/p120, ani20/p100 5 multiplier & divider, mulitiply- accumulator rl78 cpu core
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 34 of 208 aug 12, 2016 1.6 outline of functions [30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 kb to 64 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) ( note is listed on the next page.) item 30-pin 32-pin 36-pin 40-pin r5f104ax (x = a, c to e) r5f104bx (x = a, c to e) r5f104cx (x = a, c to e) r5f104ex (x = a, c to e) code flash memory (kb) 16 to 64 16 to 64 16 to 64 16 to 64 data flash memory (kb) 4444 ram (kb) 2.5 to 5.5 note 2.5 to 5.5 note 2.5 to 5.5 note 2.5 to 5.5 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscillation, exte rnal main system clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock ? xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) ? 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and accumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (s et, reset, test, and boolean operation), etc. i/o port total 26 28 32 36 cmos i/o 21 22 26 28 cmos input3335 cmos output???? n-ch open-drain i/o (6 v tolerance) 2333 timer 16-bit timer 8 channels (tau: 4 channels, timer rj: 1 channel, timer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 13 channels pwm outputs: 9 channels rtc output ? 1 ?1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 35 of 208 aug 12, 2016 note the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f104xd (x = a to c, e to g, j, l): start address fe900h r5f104xe (x = a to c, e to g, j, l): start address fe900h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 36 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 30-pin 32-pin 36-pin 40-pin r5f104ax (x = a, c to e) r5f104bx (x = a, c to e) r5f104cx (x = a, c to e) r5f104ex (x = a, c to e) clock output/buzzer output 2222 [30-pin, 32-pin, 36-pin products] ? 2.44 khz, 4.88 khz, 9.76 khz, 1. 25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) [40-pin products] ? 2.44 khz, 4.88 khz, 9.76 khz, 1. 25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 8 channels 8 channels 8 channels 9 channels serial interface [30-pin, 32-pin products] ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 chan nel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel [36-pin, 40-pin products] ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 chan nel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel 1 channel 1 channel 1 channel data transfer controller (dtc) 28 sources 29 sources event link controller (elc) event input: 19 event trigger output: 7 event input: 20 event trigger output: 7 vectored interrupt sources internal 24 24 24 24 external 6667 key interrupt ??? 4 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = ? 40 to +85c) v dd = 2.4 to 5.5 v (t a = ? 40 to +105c) operating ambient temperature t a = ? 40 to +85c (a: consumer applicat ions, d: industrial applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 37 of 208 aug 12, 2016 [30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 kb to 256 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) ( note is listed on the next page.) item 30-pin 32-pin 36-pin 40-pin r5f104ax (x = f, g) r5f104bx (x = f, g) r5f104cx (x = f, g) r5f104ex (x = f to h) code flash memory (kb) 96 to 128 96 to 128 96 to 128 96 to 192 data flash memory (kb) 8888 ram (kb) 12 to 16 note 12 to 16 note 12 to 16 note 12 to 20 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscillation, exte rnal main system clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock ? xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) ? 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and accumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (s et, reset, test, and boolean operation), etc. i/o port total 26 28 32 36 cmos i/o 21 22 26 28 cmos input3335 cmos output???? n-ch open-drain i/o (6 v tolerance) 2333 timer 16-bit timer 8 channels (tau: 4 channels, timer rj: 1 channel, timer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 13 channels pwm outputs: 9 channels rtc output ? 1 ?1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 38 of 208 aug 12, 2016 note the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f104xj (x = f, g, j, l, m, p): start address f9f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 39 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 30-pin 32-pin 36-pin 40-pin r5f104ax (x = f, g) r5f104bx (x = f, g) r5f104cx (x = f, g) r5f104ex (x = f to h) clock output/buzzer output 2222 [30-pin, 32-pin, 36-pin products] ? 2.44 khz, 4.88 khz, 9.76 khz, 1. 25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) [40-pin products] ? 2.44 khz, 4.88 khz, 9.76 khz, 1. 25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 8 channels 8 channels 8 channels 9 channels d/a converter 1 channel 2 channels comparator 2 channels serial interface [30-pin, 32-pin products] ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 chan nel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel [36-pin, 40-pin products] ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 chan nel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel 1 channel 1 channel 1 channel data transfer controller (dtc) 30 sources 31 sources event link controller (elc) event input: 21 event trigger output: 8 event input: 21, even t trigger output: 9 event input: 22 event trigger output: 9 vectored interrupt sources internal 24 24 24 24 external 6667 key interrupt ? ? ? 4 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = ? 40 to +85c) v dd = 2.4 to 5.5 v (t a = ? 40 to +105c) operating ambient temperature t a = ? 40 to +85c (a: consumer applicat ions, d: industrial applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 40 of 208 aug 12, 2016 [44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 kb to 64 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) ( note is listed on the next page.) item 44-pin 48-pin 52-pin 64-pin r5f104fx (x = a, c to e) r5f104gx (x = a, c to e) r5f104jx (x = c to e) r5f104lx (x = c to e) code flash memory (kb) 16 to 64 16 to 64 32 to 64 32 to 64 data flash memory (kb) 4 4 4 4 ram (kb) 2.5 to 5.5 note 2.5 to 5.5 note 4 to 5.5 note 4 to 5.5 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscill ation, external main sy stem clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, exte rnal subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and ac cumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o porttotal 40444858 cmos i/o 31 34 38 48 cmos input 5 5 5 5 cmos output ? 1 1 1 n-ch open-drain i/o (6 v tolerance) 4444 timer 16-bit timer 8 channels (tau: 4 channels, timer rj: 1 channel, ti mer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 13 channels pwm outputs: 9 channels rtc output 1 ? 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 41 of 208 aug 12, 2016 note the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f104xd (x = a to c, e to g, j, l): start address fe900h r5f104xe (x = a to c, e to g, j, l): start address fe900h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 42 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 44-pin 48-pin 52-pin 64-pin r5f104fx (x = a, c to e) r5f104gx (x = a, c to e) r5f104jx (x = c to e) r5f104lx (x = c to e) clock output/buzzer output 2 2 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 10 channels 10 channels 12 channels 12 channels serial interface [44-pin products] ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels [48-pin, 52-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels [64-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel 1 channel 1 channel 1 channel data transfer controller (dtc) 29 sources 30 sources 31 sources event link controller (elc) event input: 20 event trigger output: 7 vectored inter- rupt sources internal 24 24 24 24 external 7 101213 key interrupt 4 6 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = ? 40 to +85c (a: consumer applications, d: industrial applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 43 of 208 aug 12, 2016 [44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 kb to 256 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) ( note is listed on the next page.) item 44-pin 48-pin 52-pin 64-pin r5f104fx (x = f to h, j) r5f104gx (x = f to h, j) r5f104jx (x = f to h, j) r5f104lx (x = f to h, j) code flash memory (kb) 96 to 256 96 to 256 96 to 256 96 to 256 data flash memory (kb) 8 8 8 8 ram (kb) 12 to 24 note 12 to 24 note 12 to 24 note 12 to 24 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscill ation, external main sy stem clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, exte rnal subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and ac cumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o porttotal 40444858 cmos i/o 31 34 38 48 cmos input 5 5 5 5 cmos output ? 1 1 1 n-ch open-drain i/o (6 v tolerance) 4444 timer 16-bit timer 8 channels (tau: 4 channels, timer rj: 1 channel, ti mer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 14 channels pwm outputs: 9 channels rtc output 1 ? 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 44 of 208 aug 12, 2016 note the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f104xj (x = f, g, j, l, m, p): start address f9f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 45 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 44-pin 48-pin 52-pin 64-pin r5f104fx (x = f to h, j) r5f104gx (x = f to h, j) r5f104jx (x = f to h, j) r5f104lx (x = f to h, j) clock output/buzzer output 2 2 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 10 channels 10 channels 12 channels 12 channels d/a converter 2 channels comparator 2 channels serial interface [44-pin products] ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels [48-pin, 52-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels [64-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel 1 channel 1 channel 1 channel data transfer controller (dtc) 31 sources 32 sources 33 sources event link controller (elc) event input: 22 event trigger output: 9 vectored inter- rupt sources internal 24 24 24 24 external 7 101213 key interrupt 4 6 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = -40 to +85c (a: consumer applic ations, d: industrial applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 46 of 208 aug 12, 2016 [48-pin, 64-pin products (code flash memory 384 kb to 512 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) ( note is listed on the next page.) item 48-pin 64-pin r5f104gx (x = k, l) r5f104lx (x = k, l) code flash memory (kb) 384 to 512 384 to 512 data flash memory (kb) 8 8 ram (kb) 32 to 48 note 32 to 48 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscill ation, external main system clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, exte rnal subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and ac cumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 44 58 cmos i/o 34 48 cmos input 5 5 cmos output 1 1 n-ch open-drain i/o (6 v tolerance) 44 timer 16-bit timer 8 channels (tau: 4 channels, timer rj: 1 channel, ti mer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 14 channels pwm outputs: 9 channels rtc output 1 ? 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 47 of 208 aug 12, 2016 note the flash library uses ram in self-progra mming and rewriting of the data flash memory. the target products and start address of the ram areas used by the flash library are shown below. r5f104xl (x = g, l, m, p): start address f3f00h for the ram areas used by the flash library, see self ram list of flash self-programming library for rl78 family (r20ut2944) .
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 48 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 48-pin 64-pin r5f104gx (x = k, l) r5f104lx (x = k, l) clock output/buzzer output 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d converter 10 channels 12 channels d/a converter 2 channels comparator 2 channels serial interface [48-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels [64-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel 1 channel data transfer controller (dtc) 32 sources 33 sources event link controller (elc) event input: 22 event trigger output: 9 vectored interrupt sources internal 24 24 external 10 13 key interrupt 6 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = -40 to +85c (a: consumer applicat ions, d: industri al applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 49 of 208 aug 12, 2016 [80-pin, 100-pin products (code flash memory 96 kb to 256 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) note in the case of the 24 kb, this is about 23 kb when the se lf-programming function and data flash function are used (for details, see chapter 3 in the rl78/g14 user?s manual). item 80-pin 100-pin r5f104mx (x = f to h, j) r5f104px (x = f to h, j) code flash memory (kb) 96 to 256 96 to 256 data flash memory (kb) 8 8 ram (kb) 12 to 24 note 12 to 24 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscill ation, external main sy stem clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, exte rnal subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and ac cumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 74 92 cmos i/o 64 82 cmos input 5 5 cmos output 1 1 n-ch open-drain i/o (6 v tolerance) 44 timer 16-bit timer 12 channels (tau: 8 channels, timer rj: 1 channel, ti mer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 18 channels pwm outputs: 12 channels rtc output 1 ? 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 50 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. item 80-pin 100-pin r5f104mx (x = f to h, j) r5f104px (x = f to h, j) clock output/buzzer output 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d c onverter 17 channels 20 channels d/a converter 2 channels 2 channels comparator 2 channels 2 channels serial interface [80-pin, 100-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 2 channels 2 channels data transfer controller (dtc) 39 sources 39 sources event link controller (elc) event input: 26 event trigger output: 9 vectored inter- rupt sources internal 32 32 external 13 13 key interrupt 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = -40 to +85c (a: consumer applic ations, d: industrial applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 51 of 208 aug 12, 2016 [80-pin, 100-pin products (code flash memory 384 kb to 512 kb)] caution this outline describes the fu nctions at the time when peripheral i/o redirection register 0, 1 (pior0, 1) are set to 00h. (1/2) note in the case of the 48 kb, this is about 47 kb when the se lf-programming function and data flash function are used (for details, see chapter 3 in the rl78/g14 user?s manual). item 80-pin 100-pin r5f104mx (x = k, l) r5f104px (x = k, l) code flash memory (kb) 384 to 512 384 to 512 data flash memory (kb) 8 8 ram (kb) 32 to 48 note 32 to 48 note address space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscill ation, external main sy stem clock input (exclk) hs (high-speed main) mode: 1 to 20 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) high-speed on-chip oscillator clock (f ih ) hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), hs (high-speed main) mode: 1 to 16 mhz (v dd = 2.4 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 1.8 to 5.5 v), lv (low-voltage main) mode: 1 to 4 mhz (v dd = 1.6 to 5.5 v) subsystem clock xt1 (crystal) oscillation, exte rnal subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 5.5 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.03125 s (high-speed on-chip oscillator clock: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits 16 bits, 32 bits 32 bits) ? multiplication and ac cumulation (16 bits 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 74 92 cmos i/o 64 82 cmos input 5 5 cmos output 1 1 n-ch open-drain i/o (6 v tolerance) 44 timer 16-bit timer 12 channels (tau: 8 channels, timer rj: 1 channel, ti mer rd: 2 channels, timer rg: 1 channel) watchdog timer 1 channel real-time clock (rtc) 1 channel 12-bit interval timer 1 channel timer output timer outputs: 18 channels pwm outputs: 12 channels rtc output 1 ? 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/g14 1. outline r01ds0053ej0330 rev. 3.30 page 52 of 208 aug 12, 2016 (2/2) note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution is not is sued by emulation with the in -circuit emulator or on- chip debug emulator. item 80-pin 100-pin r5f104mx (x = k, l) r5f104px (x = k, l) clock output/buzzer output 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/10-bit resolution a/d c onverter 17 channels 20 channels d/a converter 2 channels 2 channels comparator 2 channels 2 channels serial interface [80-pin, 100-pin products] ? csi: 2 channels/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels i 2 c bus 2 channels 2 channels data transfer controller (dtc) 39 sources 39 sources event link controller (elc) event input: 26 event trigger output: 9 vectored inter- rupt sources internal 32 32 external 13 13 key interrupt 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.04 v (t a = ? 40 to +85c) 1.51 0.06 v (t a = ? 40 to +105c) ? power-down-reset: 1.50 0.04 v (t a = ? 40 to +85c) 1.50 0.06 v (t a = ? 40 to +105c) voltage detector 1.63 v to 4.06 v (14 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 5.5 v (t a = -40 to +85c) v dd = 2.4 to 5.5 v (t a = -40 to +105c) operating ambient temperature t a = -40 to +85c (a: consumer applic ations, d: industrial applications), t a = -40 to +105c (g: industrial applications)
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 53 of 208 aug 12, 2016 2. electrical specifications (t a = -40 to +85 c) this chapter describes the following electrical specifications. target products a: consumer applications t a = -40 to +85 c r5f104xxaxx d: industrial applications t a = -40 to +85 c r5f104xxdxx g: industrial applications when t a = -40 to +105 c products is used in the range of t a = -40 to +85c r5f104xxgxx caution 1. the rl78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. caution 2. with products not provided with an ev dd0 , ev dd1 , ev ss0 , or ev ss1 pin, replace ev dd0 and ev dd1 with v dd , or replace ev ss0 and ev ss1 with v ss . caution 3. the pins mounted depend on the product. refer to 2.1 port functions to 2.2.1 functions for each product in the rl78/g14 user?s manual .
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 54 of 208 aug 12, 2016 2.1 absolute maximum ratings note 1. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. note 2. must be 6.5 v or lower. note 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark 1. unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. remark 2. av ref (+): + side reference voltage of the a/d converter. remark 3. v ss : reference voltage absolute maximum ratings (1/2) parameter symbols conditions ratings unit supply voltage v dd -0.5 to +6.5 v ev dd0 , ev dd1 ev dd0 = ev dd1 -0.5 to +6.5 v ev ss0 , ev ss1 ev ss0 = ev ss1 -0.5 to +0.3 v regc pin input voltage v iregc regc -0.3 to +2.8 and -0.3 to v dd +0.3 note 1 v input voltage v i1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 -0.3 to ev dd0 +0.3 and -0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) -0.3 to +6.5 v v i3 p20 to p27, p121 to p124, p137, p150 to p156, exclk, exclks, reset -0.3 to v dd +0.3 note 2 v output voltage v o1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 -0.3 to ev dd0 +0.3 and -0.3 to v dd +0.3 note 2 v v o2 p20 to p27, p150 to p156 -0.3 to v dd +0.3 note 2 v analog input voltage v ai1 ani16 to ani20 -0.3 to ev dd0 +0.3 and -0.3 to av ref (+) +0.3 notes 2, 3 v v ai2 ani0 to ani14 -0.3 to v dd +0.3 and -0.3 to av ref (+) +0.3 notes 2, 3 v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 55 of 208 aug 12, 2016 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. absolute maximum ratings (2/2) parameter symbols conditions ratings unit output current, high i oh1 per pin p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 -40 ma total of all pins -170 ma p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 -70 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 -100 ma i oh2 per pin p20 to p27, p150 to p156 -0.5 ma total of all pins -2 ma output current, low i ol1 per pin p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 40 ma total of all pins 170 ma p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 70 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 100 ma i ol2 per pin p20 to p27, p150 to p156 1 ma total of all pins 5ma operating ambient tem- perature t a in normal operation mode -40 to +85 c in flash memory programming mode storage temperature t stg -65 to +150 c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 56 of 208 aug 12, 2016 2.2 oscillator characteristics 2.2.1 x1, xt1 characteristics note indicates only permissible oscillat or frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscilla tor circuit mounted on a boa rd to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator and xt1 oscillator, refer to 5.4 system clock oscillator in the rl78/g14 user?s manual. 2.2.2 on-chip oscillator characteristics note 1. high-speed on-chip oscillator fr equency is selected with bits 0 to 4 of the opt ion byte (000c2h) and bits 0 to 2 of the hocodiv register. note 2. this only indicates t he oscillator characte ristics. refer to ac characteristics for instruction execution time. (t a = -40 to +85c, 1.6 v v dd 5.5 v, v ss = 0 v) resonator resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 1.8 v v dd < 2.4 v 1.0 8.0 1.6 v v dd < 1.8 v 1.0 4.0 xt1 clock oscillation frequency (f xt ) note crystal resonator 32 32.768 35 khz (t a = -40 to +85c, 1.6 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 132mhz high-speed on-chip oscillator clock frequency accuracy -20 to +85c 1.8 v v dd 5.5 v -1.0 +1.0 % 1.6 v v dd < 1.8 v -5.0 +5.0 % -40 to -20c 1.8 v v dd < 5.5 v -1.5 +1.5 % 1.6 v v dd < 1.8 v -5.5 +5.5 % low-speed on-chip oscilla tor clock frequency f il 15 khz low-speed on-chip oscilla tor clock frequency accuracy -15 +15 %
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 57 of 208 aug 12, 2016 2.3 dc characteristics 2.3.1 pin characteristics note 1. value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , ev dd1 , v dd pins to an output pin. note 2. do not exceed the total current value. note 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be ca lculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = -10.0 ma total output current of pins = (-10.0 0.7)/(80 0.01) -8.7 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. note 4. -100 ma for industrial applicati ons (r5f104xxdxx, r5f104xxgxx). caution p00, p02 to p04, p10, p11, p13 to p15, p17, p30, p43 to p45, p50 to p55, p71, p74, p80 to p82, and p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 1.6 v ev dd0 5.5 v -10.0 note 2 ma total of p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v -55.0 ma 2.7 v ev dd0 < 4.0 v -10.0 ma 1.8 v ev dd0 < 2.7 v -5.0 ma 1.6 v ev dd0 < 1.8 v -2.5 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v -80.0 ma 2.7 v ev dd0 < 4.0 v -19.0 ma 1.8 v ev dd0 < 2.7 v -10.0 ma 1.6 v ev dd0 < 1.8 v -5.0 ma total of all pins (when duty 70% note 3 ) 1.6 v ev dd0 5.5 v -135.0 note 4 ma i oh2 per pin for p20 to p27, p150 to p156 1.6 v v dd 5.5 v -0.1 note 2 ma total of all pins (when duty 70% note 3 ) 1.6 v v dd 5.5 v -1.5 ma
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 58 of 208 aug 12, 2016 note 1. value of current at which the device operation is guaranteed even if the current flows from an output pin to the ev ss0 , ev ss1 , and v ss pins. note 2. do not exceed the total current value. note 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be ca lculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pins = (10.0 0.7)/(80 0.01) 8.7 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/5) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 20.0 note 2 ma per pin for p60 to p63 15.0 note 2 ma total of p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v 70.0 ma 2.7 v ev dd0 < 4.0 v 15.0 ma 1.8 v ev dd0 < 2.7 v 9.0 ma 1.6 v ev dd0 < 1.8 v 4.5 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v 80.0 ma 2.7 v ev dd0 < 4.0 v 35.0 ma 1.8 v ev dd0 < 2.7 v 20.0 ma 1.6 v ev dd0 < 1.8 v 10.0 ma total of all pins (when duty 70% note 3 ) 150.0 ma i ol2 per pin for p20 to p27, p150 to p156 0.4 note 2 ma total of all pins (when duty 70% note 3 ) 1.6 v v dd 5.5 v 5.0 ma
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 59 of 208 aug 12, 2016 caution the maximum value of v ih of pins p00, p02 to p04, p10, p11, p13 to p15, p17, p30, p43 to p45, p50 to p55, p71, p74, p80 to p82, and p142 to p144 is ev dd0 , even in the n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (3/5) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 normal input buffer 0.8 ev dd0 ev dd0 v v ih2 p01, p03, p04, p10, p14 to p17, p30, p43, p44, p50, p53 to p55, p80, p81, p142, p143 ttl input buffer 4.0 v ev dd0 5.5 v 2.2 ev dd0 v ttl input buffer 3.3 v ev dd0 < 4.0 v 2.0 ev dd0 v ttl input buffer 1.6 v ev dd0 < 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p156 0.7 v dd v dd v v ih4 p60 to p63 0.7 ev dd0 6.0 v v ih5 p121 to p124, p137, exclk, exclks, reset 0.8 v dd v dd v input voltage, low v il1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 normal input buffer 0 0.2 ev dd0 v v il2 p01, p03, p04, p10, p14 to p17, p30, p43, p44, p50, p53 to p55, p80, p81, p142, p143 ttl input buffer 4.0 v ev dd0 5.5 v 00.8v ttl input buffer 3.3 v ev dd0 < 4.0 v 00.5v ttl input buffer 1.6 v ev dd0 < 3.3 v 00.32v v il3 p20 to p27, p150 to p156 0 0.3 v dd v v il4 p60 to p63 0 0.3 ev dd0 v v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2 v dd v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 60 of 208 aug 12, 2016 caution p00, p02 to p04, p10, p11, p13 to p15, p17, p30, p43 to p45, p50 to p55, p71, p74, p80 to p82, p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (4/5) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 4.0 v ev dd0 5.5 v, i oh1 = -10.0 ma ev dd0 - 1.5 v 4.0 v ev dd0 5.5 v, i oh1 = -3.0 ma ev dd0 - 0.7 v 1.8 v ev dd0 5.5 v, i oh1 = -1.5 ma ev dd0 - 0.5 v 1.6 v ev dd0 < 1.8 v, i oh1 = -1.0 ma ev dd0 - 0.5 v v oh2 p20 to p27, p150 to p156 1.6 v v dd 5.5 v, i oh2 = -100 a v dd - 0.5 v output voltage, low v ol1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 4.0 v ev dd0 5.5 v, i ol1 = 20.0 ma 1.3 v 4.0 v ev dd0 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v ev dd0 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v ev dd0 5.5 v, i ol1 = 1.5 ma 0.4 v 1.8 v ev dd0 5.5 v, i ol1 = 0.6 ma 0.4 v 1.6 v ev dd0 5.5 v, i ol1 = 0.3 ma 0.4 v v ol2 p20 to p27, p150 to p156 1.6 v v dd 5.5 v, i ol2 = 400 a 0.4 v v ol3 p60 to p63 4.0 v ev dd0 5.5 v, i ol3 = 15.0 ma 2.0 v 4.0 v ev dd0 5.5 v, i ol3 = 5.0 ma 0.4 v 2.7 v ev dd0 5.5 v, i ol3 = 3.0 ma 0.4 v 1.8 v ev dd0 5.5 v, i ol3 = 2.0 ma 0.4 v 1.6 v ev dd0 5.5 v, i ol3 = 1.0 ma 0.4 v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 61 of 208 aug 12, 2016 remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (5/5) items symbol conditions min. typ. max. unit input leakage cur- rent, high i lih1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 v i = ev dd0 1 a i lih2 p20 to p27, p137, p150 to p156, reset v i = v dd 1 a i lih3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v dd in input port or external clock input 1 a in resonator con- nection 10 a input leakage current, low i lil1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 v i = ev ss0 -1 a i lil2 p20 to p27, p137, p150 to p156, reset v i = v ss -1 a i lil3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v ss in input port or external clock input -1 a in resonator con- nection -10 a on-chip pull-up resistance r u p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 v i = ev ss0 , in input port 10 20 100 k
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 62 of 208 aug 12, 2016 2.3.2 supply current characteristics ( notes and remarks are listed on the next page.) (1) flash rom: 16 to 64 kb of 30- to 64-pin products (t a = -40 to +85c, 1.6 v ev dd0 v dd 5.5 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operat- ing mode hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.4 ma v dd = 3.0 v 2.4 f hoco = 32 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.1 v dd = 3.0 v 2.1 hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.1 8.7 ma v dd = 3.0 v 5.1 8.7 f hoco = 32 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 4.8 8.1 v dd = 3.0 v 4.8 8.1 f hoco = 48 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.0 6.9 v dd = 3.0 v 4.0 6.9 f hoco = 24 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 3.8 6.3 v dd = 3.0 v 3.8 6.3 f hoco = 16 mhz, f ih = 16 mhz note 3 normal operation v dd = 5.0 v 2.8 4.6 v dd = 3.0 v 2.8 4.6 ls (low-speed main) mode note 5 f hoco = 8 mhz, f ih = 8 mhz note 3 normal operation v dd = 3.0 v 1.3 2.0 ma v dd = 2.0 v 1.3 2.0 lv (low-voltage main) mode note 5 f hoco = 4 mhz, f ih = 4 mhz note 3 normal operation v dd = 3.0 v 1.3 1.8 ma v dd = 2.0 v 1.3 1.8 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.3 5.3 ma resonator connection 3.4 5.5 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.3 5.3 resonator connection 3.4 5.5 f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 2.0 3.1 resonator connection 2.1 3.2 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.0 3.1 resonator connection 2.1 3.2 ls (low-speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 3.0 v normal operation square wave input 1.2 1.9 ma resonator connection 1.2 2.0 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation square wave input 1.2 1.9 resonator connection 1.2 2.0 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 4.7 6.1 a resonator connection 4.7 6.1 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 4.7 6.1 resonator connection 4.7 6.1 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 4.8 6.7 resonator connection 4.8 6.7 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 4.8 7.5 resonator connection 4.8 7.5 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 5.4 8.9 resonator connection 5.4 8.9
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 63 of 208 aug 12, 2016 note 1. total current flowing into v dd and ev dd0 , including the input leakage current flow ing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d conv erter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the rtc, 12-bit interval timer, and watchdog timer. note 5. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 64 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (1) flash rom: 16 to 64 kb of 30- to 64-pin products (t a = -40 to +85c, 1.6 v ev dd0 v dd 5.5 v, v ss = ev ss0 = 0 v)(2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 64 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.80 3.09 ma v dd = 3.0 v 0.80 3.09 f hoco = 32 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.49 2.40 v dd = 3.0 v 0.49 2.40 f hoco = 48 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.62 2.40 v dd = 3.0 v 0.62 2.40 f hoco = 24 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.4 1.83 v dd = 3.0 v 0.4 1.83 f hoco = 16 mhz, f ih = 16 mhz note 4 v dd = 5.0 v 0.37 1.38 v dd = 3.0 v 0.37 1.38 ls (low-speed main) mode note 7 f hoco = 8 mhz, f ih = 8 mhz note 4 v dd = 3.0 v 260 710 a v dd = 2.0 v 260 710 lv (low-voltage main) mode note 7 f hoco = 4 mhz, f ih = 4 mhz note 4 v dd = 3.0 v 420 700 a v dd = 2.0 v 420 700 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.28 1.55 ma resonator connection 0.40 1.74 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.28 1.55 resonator connection 0.40 1.74 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.19 0.86 resonator connection 0.25 0.93 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.19 0.86 resonator connection 0.25 0.93 ls (low-speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 3.0 v square wave input 95 550 a resonator connection 140 590 f mx = 8 mhz note 3 , v dd = 2.0 v square wave input 95 550 resonator connection 140 590 subsystem clock operation f sub = 32.768 khz note 5 , t a = -40c square wave input 0.25 0.57 a resonator connection 0.44 0.76 f sub = 32.768 khz note 5 , t a = +25c square wave input 0.30 0.57 resonator connection 0.49 0.76 f sub = 32.768 khz note 5 , t a = +50c square wave input 0.36 1.17 resonator connection 0.59 1.36 f sub = 32.768 khz note 5 , t a = +70c square wave input 0.49 1.97 resonator connection 0.72 2.16 f sub = 32.768 khz note 5 , t a = +85c square wave input 0.97 3.37 resonator connection 1.16 3.56 i dd3 note 6 stop mode note 8 t a = -40c 0.18 0.51 a t a = +25c 0.24 0.51 t a = +50c 0.29 1.10 t a = +70c 0.41 1.90 t a = +85c 0.90 3.30
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 65 of 208 aug 12, 2016 note 1. total current flowing into v dd and ev dd0 , including the input leakage current flow ing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d conv erter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit inte rval timer and watchdog timer. note 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 66 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operat- ing mode hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.6 ma v dd = 3.0 v 2.6 f hoco = 32 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.3 v dd = 3.0 v 2.3 hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.4 10.2 ma v dd = 3.0 v 5.4 10.2 f hoco = 32 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.0 9.6 v dd = 3.0 v 5.0 9.6 f hoco = 48 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.2 7.8 v dd = 3.0 v 4.2 7.8 f hoco = 24 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.0 7.4 v dd = 3.0 v 4.0 7.4 f hoco = 16 mhz, f ih = 16 mhz note 3 normal operation v dd = 5.0 v 3.0 5.3 v dd = 3.0 v 3.0 5.3 ls (low-speed main) mode note 5 f hoco = 8 mhz, f ih = 8 mhz note 3 normal operation v dd = 3.0 v 1.4 2.3 ma v dd = 2.0 v 1.4 2.3 lv (low-voltage main) mode note 5 f hoco = 4 mhz, f ih = 4 mhz note 3 normal operation v dd = 3.0 v 1.3 1.9 ma v dd = 2.0 v 1.3 1.9 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.4 6.2 ma resonator connection 3.6 6.4 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.4 6.2 resonator connection 3.6 6.4 f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 2.1 3.6 resonator connection 2.2 3.7 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.1 3.6 resonator connection 2.2 3.7 ls (low-speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 3.0 v normal operation square wave input 1.2 2.2 ma resonator connection 1.2 2.3 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation square wave input 1.2 2.2 resonator connection 1.2 2.3 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 4.9 7.1 a resonator connection 4.9 7.1 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 4.9 7.1 resonator connection 4.9 7.1 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 5.1 8.8 resonator connection 5.1 8.8 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 5.5 10.5 resonator connection 5.5 10.5 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 6.5 14.5 resonator connection 6.5 14.5
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 67 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillat ion). however, not including the current flowing into the 12-bit interval timer and watchdog timer. note 5. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 68 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply cur- rent note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 64 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.79 3.32 ma v dd = 3.0 v 0.79 3.32 f hoco = 32 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.49 2.63 v dd = 3.0 v 0.49 2.63 f hoco = 48 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.62 2.57 v dd = 3.0 v 0.62 2.57 f hoco = 24 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.4 2.00 v dd = 3.0 v 0.4 2.00 f hoco = 16 mhz, f ih = 16 mhz note 4 v dd = 5.0 v 0.38 1.49 v dd = 3.0 v 0.38 1.49 ls (low-speed main) mode note 7 f hoco = 8 mhz, f ih = 8 mhz note 4 v dd = 3.0 v 250 800 a v dd = 2.0 v 250 800 lv (low-voltage main) mode note 7 f hoco = 4 mhz, f ih = 4 mhz note 4 v dd = 3.0 v 420 755 a v dd = 2.0 v 420 755 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.30 1.63 ma resonator connection 0.40 1.85 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.30 1.63 resonator connection 0.40 1.85 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.20 0.89 resonator connection 0.25 0.97 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.20 0.89 resonator connection 0.25 0.97 ls (low-speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 3.0 v square wave input 110 580 a resonator connection 140 630 f mx = 8 mhz note 3 , v dd = 2.0 v square wave input 110 580 resonator connection 140 630 subsystem clock oper- ation f sub = 32.768 khz note 5 , t a = -40c square wave input 0.28 0.66 a resonator connection 0.47 0.85 f sub = 32.768 khz note 5 , t a = +25c square wave input 0.34 0.66 resonator connection 0.53 0.85 f sub = 32.768 khz note 5 , t a = +50c square wave input 0.37 2.35 resonator connection 0.56 2.54 f sub = 32.768 khz note 5 , t a = +70c square wave input 0.61 4.08 resonator connection 0.80 4.27 f sub = 32.768 khz note 5 , t a = +85c square wave input 1.55 8.09 resonator connection 1.74 8.28 i dd3 note 6 stop mode note 8 t a = -40c 0.19 0.57 a t a = +25c 0.25 0.57 t a = +50c 0.33 2.26 t a = +70c 0.52 3.99 t a = +85c 1.46 8.00
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 69 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit inte rval timer and watchdog timer. note 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 70 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (3) flash rom: 384 to 512 kb of 48- to 100-pin products (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operat- ing mode hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.9 ma v dd = 3.0 v 2.9 f hoco = 32 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.5 v dd = 3.0 v 2.5 hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 6.0 11.2 ma v dd = 3.0 v 6.0 11.2 f hoco = 32 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.5 10.6 v dd = 3.0 v 5.5 10.6 f hoco = 48 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.7 8.6 v dd = 3.0 v 4.7 8.6 f hoco = 24 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.4 8.2 v dd = 3.0 v 4.4 8.2 f hoco = 16 mhz, f ih = 16 mhz note 3 normal operation v dd = 5.0 v 3.3 5.9 v dd = 3.0 v 3.3 5.9 ls (low-speed main) mode note 5 f hoco = 8 mhz, f ih = 8 mhz note 3 normal operation v dd = 3.0 v 1.5 2.5 ma v dd = 2.0 v 1.5 2.5 lv (low-voltage main) mode note 5 f hoco = 4 mhz, f ih = 4 mhz note 3 normal operation v dd = 3.0 v 1.5 2.1 ma v dd = 2.0 v 1.5 2.1 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.7 6.8 ma resonator connection 3.9 7.0 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.7 6.8 resonator connection 3.9 7.0 f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 2.3 4.1 resonator connection 2.3 4.2 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.3 4.1 resonator connection 2.3 4.2 ls (low-speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 3.0 v normal operation square wave input 1.4 2.4 ma resonator connection 1.4 2.5 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation square wave input 1.4 2.4 resonator connection 1.4 2.5 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 5.2 a resonator connection 5.2 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 5.3 7.7 resonator connection 5.3 7.7 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 5.5 10.6 resonator connection 5.5 10.6 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 5.9 13.2 resonator connection 6.0 13.2 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 6.8 17.5 resonator connection 6.9 17.5
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 71 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillat ion). however, not including the current flowing into the 12-bit interval timer and watchdog timer. note 5. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 72 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (3) flash rom: 384 to 512 kb of 48- to 100-pin products (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply cur- rent note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 64 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.93 3.32 ma v dd = 3.0 v 0.93 3.32 f hoco = 32 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.5 2.63 v dd = 3.0 v 0.5 2.63 f hoco = 48 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.72 2.60 v dd = 3.0 v 0.72 2.60 f hoco = 24 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.42 2.03 v dd = 3.0 v 0.42 2.03 f hoco = 16 mhz, f ih = 16 mhz note 4 v dd = 5.0 v 0.39 1.50 v dd = 3.0 v 0.39 1.50 ls (low-speed main) mode note 7 f hoco = 8 mhz, f ih = 8 mhz note 4 v dd = 3.0 v 270 800 a v dd = 2.0 v 270 800 lv (low-voltage main) mode note 7 f hoco = 4 mhz, f ih = 4 mhz note 4 v dd = 3.0 v 450 755 a v dd = 2.0 v 450 755 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.31 1.69 ma resonator connection 0.41 1.91 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.31 1.69 resonator connection 0.41 1.91 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.21 0.94 resonator connection 0.26 1.02 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.21 0.94 resonator connection 0.26 1.02 ls (low-speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 3.0 v square wave input 110 610 a resonator connection 150 660 f mx = 8 mhz note 3 , v dd = 2.0 v square wave input 110 610 resonator connection 150 660 subsystem clock oper- ation f sub = 32.768 khz note 5 , t a = -40c square wave input 0.31 a resonator connection 0.50 f sub = 32.768 khz note 5 , t a = +25c square wave input 0.38 0.76 resonator connection 0.57 0.95 f sub = 32.768 khz note 5 , t a = +50c square wave input 0.47 3.59 resonator connection 0.70 3.78 f sub = 32.768 khz note 5 , t a = +70c square wave input 0.80 6.20 resonator connection 1.00 6.39 f sub = 32.768 khz note 5 , t a = +85c square wave input 1.65 10.56 resonator connection 1.84 10.75 i dd3 note 6 stop mode note 8 t a = -40c 0.19 a t a = +25c 0.30 0.59 t a = +50c 0.41 3.42 t a = +70c 0.80 6.03 t a = +85c 1.53 10.39
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 73 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit inte rval timer and watchdog timer. note 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 74 of 208 aug 12, 2016 note 1. current flowing to v dd . note 2. when high speed on-chip oscillator and high-speed system clock are stopped. note 3. current flowing only to the real-time cl ock (rtc) (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 micr ocontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or ha lt mode. when th e low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation in cludes the operational current of the real-time clock. note 4. current flowing only to the 12-bit interv al timer (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. (4) peripheral functions (common to all products) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit low-speed on-chip oscilla- tor operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operat- ing current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating cur- rent i adc notes 1, 6 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref note 1 75.0 a temperature sensor operat- ing current i tmps note 1 75.0 a d/a converter operating cur- rent i dac notes 1, 11, 13 per d/a converter channel 1.5 ma comparator operating cur- rent i cmp notes 1, 12, 13 v dd = 5.0 v, regulator output voltage = 2.1 v window mode 12.5 a comparator high-speed mode 6.5 a comparator low-speed mode 1.7 a v dd = 5.0 v, regulator output voltage = 1.8 v window mode 8.0 a comparator high-speed mode 4.0 a comparator low-speed mode 1.3 a lvd operating current i lvd notes 1, 7 0.08 a self-programming operat- ing current i fsp notes 1, 9 2.50 12.20 ma bgo operating current i bgo notes 1, 8 2.50 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 10 0.50 0.60 ma the a/d conversion opera- tions are performed, low volt- age mode, av refp = v dd = 3.0 v 1.20 1.44 csi/uart operation 0.70 0.84 dtc operation 3.10
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 75 of 208 aug 12, 2016 note 5. current flowing only to the watchdog timer (including th e operating current of the low-speed on-chip oscillator). the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer is in operation. note 6. current flowing only to the a/d conver ter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. note 7. current flowing only to the lvd circuit. the supply curre nt of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. note 8. current flowing during programming of the data flash. note 9. current flowing during self-programming. note 10. for shift time to the snooze mode, see 23.3.3 snooze mode in the rl78/g14 user?s manual. note 11. current flowing only to the d/a conver ter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i dac when the d/a converter operates in an operation mode or the halt mode. note 12. current flowing only to the comparator circuit. the supply current of the r l78 microcontrollers is the sum of i dd1 , i dd2 , or i dd3 and i cmp when the comparator circuit is in operation. note 13. a comparator and d/a converter are provided in products with 96 kb or more code flash memory. remark 1. f il : low-speed on-chip oscillator clock frequency remark 2. f sub : subsystem clock frequency (x t1 clock oscillation frequency) remark 3. f clk : cpu/peripheral hardware clock frequency remark 4. temperature condition of the typ. value is t a = 25c
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 76 of 208 aug 12, 2016 2.4 ac characteristics note the following conditions are required for low voltage interface when ev dd0 < v dd 1.8 v ev dd0 < 2.7 v: min. 125 ns 1.6 v ev dd0 < 1.8 v: min. 250 ns remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn bit of timer mode register mn (tmrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3)) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) items symbol conditions min. typ. max. unit instruction cycle (min- imum instruction exe- cution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v v dd 5.5 v 0.03125 1 s 2.4 v v dd < 2.7 v 0.0625 1 s ls (low-speed main) mode 1.8 v v dd 5.5 v 0.125 1 s lv (low-voltage main) mode 1.6 v v dd 5.5 v 0.25 1 s subsystem clock (f sub ) operation 1.8 v v dd 5.5 v 28.5 30.5 31.3 s in the self- program- ming mode hs (high-speed main) mode 2.7 v v dd 5.5 v 0.03125 1 s 2.4 v v dd < 2.7 v 0.0625 1 s ls (low-speed main) mode 1.8 v v dd 5.5 v 0.125 1 s lv (low-voltage main) mode 1.8 v v dd 5.5 v 0.25 1 s external system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd 2.7 v 1.0 16.0 mhz 1.8 v v dd < 2.4 v 1.0 8.0 mhz 1.6 v v dd < 1.8 v 1.0 4.0 mhz f exs 32 35 khz external system clock input high-level width, low-level width t exh , t exl 2.7 v v dd 5.5 v 24 ns 2.4 v v dd 2.7 v 30 ns 1.8 v v dd < 2.4 v 60 ns 1.6 v v dd < 1.8 v 120 ns t exhs , t exls 13.7 s ti00 to ti03, ti10 to ti13 input high-level width, low-level width t tih , t til 1/f mck + 10 note ns timer rj input cycle f c trjio 2.7 v ev dd0 5.5 v 100 ns 1.8 v ev dd0 < 2.7 v 300 ns 1.6 v ev dd0 < 1.8 v 500 ns timer rj input high- level width, low-level width t tjih , t tjil trjio 2.7 v ev dd0 5.5 v 40 ns 1.8 v ev dd0 < 2.7 v 120 ns 1.6 v ev dd0 < 1.8 v 200 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 77 of 208 aug 12, 2016 (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) items symbol conditions min. typ. max. unit timer rd input high-level width, low-level width t tdih , t tdil trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 3/f clk ns timer rd forced cutoff signal input low-level width t tdsil p130/intp0 2mhz < f clk 32 mhz 1 s f clk 2 mhz 1/f clk + 1 timer rg input high-level width, low-level width t tgih , t tgil trgioa, trgiob 2.5/f clk ns to00 to to03, to10 to to13, trjio0, trjo0, trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1, trgioa, trgiob output frequency f to hs (high-speed main) mode 4.0 v ev dd0 5.5 v 16 mhz 2.7 v ev dd0 < 4.0 v 8 mhz 1.8 v ev dd0 < 2.7 v 4 mhz 1.6 v ev dd0 < 1.8 v 2 mhz ls (low-speed main) mode 1.8 v ev dd0 5.5 v 4 mhz 1.6 v ev dd0 < 1.8 v 2 mhz lv (low-voltage main) mode 1.6 v ev dd0 5.5 v 2mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 4.0 v ev dd0 5.5 v 16 mhz 2.7 v ev dd0 < 4.0 v 8 mhz 1.8 v ev dd0 < 2.7 v 4 mhz 1.6 v ev dd0 < 1.8 v 2 mhz ls (low-speed main) mode 1.8 v ev dd0 5.5 v 4 mhz 1.6 v ev dd0 < 1.8 v 2 mhz lv (low-voltage main) mode 1.8 v ev dd0 5.5 v 4 mhz 1.6 v ev dd0 < 1.8 v 2 mhz interrupt input high-level width, low-level width t inth , t intl intp0 1.6 v v dd 5.5 v 1 s intp1 to intp11 1.6 v ev dd0 5.5 v 1 s key interrupt input low-level width t kr kr0 to kr7 1.8 v ev dd0 5.5 v 250 ns 1.6 v ev dd0 < 1.8 v 1 s reset low-level width t rsl 10 s
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 78 of 208 aug 12, 2016 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.03125 0.0625 0.05 cycle time t cy [s] supply voltage v dd [v] during self-programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 79 of 208 aug 12, 2016 t cy vs v dd (ls (low-speed main) mode) t cy vs v dd (lv (low-voltage main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 5.5 0.01 cycle time t cy [s] supply voltage v dd [v] 1.8 6.0 0.125 during self-programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 0.01 cycle time t cy [s] supply voltage v dd [v] 1.6 6.0 1.8 5.5 0.25 during self-programming when high-speed system clock is selected when the high-speed on-chip os cillator clock is selected
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 80 of 208 aug 12, 2016 ac timing test points external system clock timing ti/to timing v ih /v oh v il /v ol v ih /v oh test points v il /v ol exclk/exclks 1/f ex 1/f exs t exl t exls t exh t exhs t til t tih 1/f to ti00 to ti03, ti10 to ti13 to00 to to03, to10 to to13, trjio0, trjo0, trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1, trgioa, trgiob
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 81 of 208 aug 12, 2016 t tjil trjio t tjih t tdil trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 t tdih t tdsil intp0 t tgil trgioa, trgiob t tgih
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 82 of 208 aug 12, 2016 interrupt request input timing key interrupt input timing reset input timing intp0 to intp11 t intl t inth t kr kr0 to kr7 t rsl reset
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 83 of 208 aug 12, 2016 2.5 peripheral functions characteristics ac timing test points 2.5.1 serial array unit note 1. transfer rate in the snooze mode is 4800 bps only. however, the snooze mode cannot be used when frqsel4 = 1. note 2. the following conditions are required for low voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v: max. 2.6 mbps 1.8 v ev dd0 < 2.4 v: max. 1.3 mbps 1.6 v ev dd0 < 1.8 v: max. 0.6 mbps note 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (1.8 v v dd 5.5 v) lv (low-voltage main) mode: 4 mhz (1.6 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). (1) during communication at same potential (uart mode) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. transfer rate note 1 2.4 v ev dd0 5.5 v f mck /6 note 2 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 5.3 1.3 0.6 mbps 1.8 v ev dd0 5.5 v f mck /6 note 2 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 5.3 1.3 0.6 mbps 1.7 v ev dd0 5.5 v f mck /6 note 2 f mck /6 note 2 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 5.3 1.3 0.6 mbps 1.6 v ev dd0 5.5 v ? f mck /6 note 2 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 ? 1.3 0.6 mbps v ih /v oh v il /v ol v ih /v oh test points v il /v ol
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 84 of 208 aug 12, 2016 uart mode connection diagram (durin g communication at same potential) uart mode bit width (durin g communication at same potential) (reference) remark 1. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 5, 14) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) rl78 microcontroller txdq rxdq user?s device rx tx baud rate error tolerance txdq rxdq high-/low-bit width 1/transfer rate
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 85 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. this value is valid only w hen csi00?s peripheral i/o redirect function is not used. remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom numbers (g = 1) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) (2) during communication at same potential (csi mode ) (master mode, sckp... internal clock output, corre- sponding csi00 only) (t a = -40 to +85c, 2.7 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 2/f clk 4.0 v ev dd0 5.5 v 62.5 250 500 ns 2.7 v ev dd0 5.5 v 83.3 250 500 ns sckp high-/low-level width t kh1 , t kl1 4.0 v ev dd0 5.5 v t kcy1 /2 - 7 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.7 v ev dd0 5.5 v t kcy1 /2 - 10 t kcy1 /2 - 50 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 4.0 v ev dd0 5.5 v 23 110 110 ns 2.7 v ev dd0 5.5 v 33 110 110 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v ev dd0 5.5 v 10 10 10 ns delay time from sckp to sop output note 3 t kso1 c = 20 pf note 4 10 10 10 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 86 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0, 1, 3 to 5, 14) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (3) during communication at same potential (csi mo de) (master mode, sckp... internal clock output) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v e vdd0 5.5 v 125 500 1000 ns 2.4 v ev dd0 5.5 v 250 500 1000 ns 1.8 v ev dd0 5.5 v 500 500 1000 ns 1.7 v ev dd0 5.5 v 1000 1000 1000 ns 1.6 v ev dd0 5.5 v ? 1000 1000 ns sckp high-/low-level width t kh1 , t kl1 4.0 v ev dd0 5.5 v t kcy1 /2 - 12 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.7 v ev dd0 5.5 v t kcy1 /2 - 18 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.4 v ev dd0 5.5 v t kcy1 /2 - 38 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 1.8 v ev dd0 5.5 v t kcy1 /2 - 50 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 1.7 v ev dd0 5.5 v t kcy1 /2 - 100 t kcy1 /2 - 100 t kcy1 /2 - 100 ns 1.6 v ev dd0 5.5 v ?t kcy1 /2 - 100 t kcy1 /2 - 100 ns sip setup time (to sckp ) note 1 t sik1 4.0 v ev dd0 5.5 v 44 110 110 ns 2.7 v ev dd0 5.5 v 44 110 110 ns 2.4 v ev dd0 5.5 v 75 110 110 ns 1.8 v ev dd0 5.5 v 110 110 110 ns 1.7 v ev dd0 5.5 v 220 220 220 ns 1.6 v ev dd0 5.5 v ?220220ns sip hold time (from sckp ) note 2 t ksi1 1.7 v ev dd0 5.5 v 19 19 19 ns 1.6 v ev dd0 5.5 v ?1919ns delay time from sckp to sop output note 3 t kso1 1.7 v ev dd0 5.5 v c = 30 pf note 4 25 25 25 ns 1.6 v ev dd0 5.5 v c = 30 pf note 4 ?2525ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 87 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sop output lines. note 5. the maximum transfer rate when using the snooze mode is 1 mbps. caution select the normal input buffer for the sip pin and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). (4) during communication at same potential (csi mode) (slave mode , sckp... external clock input) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time note 5 t kcy2 4.0 v ev dd0 5.5 v 20 mhz < f mck 8/f mck ??ns f mck 20 mhz 6/f mck 6/f mck 6/f mck ns 2.7 v ev dd0 5.5 v 16 mhz < f mck 8/f mck ??ns f mck 16 mhz 6/f mck 6/f mck 6/f mck ns 2.4 v ev dd0 5.5 v 6/f mck and 500 6/f mck and 500 6/f mck and 500 ns 1.8 v ev dd0 5.5 v 6/f mck and 750 6/f mck and 750 6/f mck and 750 ns 1.7 v ev dd0 5.5 v 6/f mck and 1500 6/f mck and 1500 6/f mck and 1500 ns 1.6 v ev dd0 5.5 v ?6/f mck and 1500 6/f mck and 1500 ns sckp high-/ low-level width t kh2 , t kl2 4.0 v ev dd0 5.5 v t kcy2 /2 - 7 t kcy2 /2 - 7 t kcy2 /2 - 7 ns 2.7 v ev dd0 5.5 v t kcy2 /2 - 8 t kcy2 /2 - 8 t kcy2 /2 - 8 ns 1.8 v ev dd0 5.5 v t kcy2 /2 - 18 t kcy2 /2 - 18 t kcy2 /2 - 18 ns 1.7 v ev dd0 5.5 v t kcy2 /2 - 66 t kcy2 /2 - 66 t kcy2 /2 - 66 ns 1.6 v ev dd0 5.5 v ?t kcy2 /2 - 66 t kcy2 /2 - 66 ns sip setup time (to sckp ) note 1 t sik2 2.7 v ev dd0 5.5 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns 1.8 v ev dd0 5.5 v 1/f mck + 30 1/f mck + 30 1/f mck + 30 ns 1.7 v ev dd0 5.5 v 1/f mck + 40 1/f mck + 40 1/f mck + 40 ns 1.6 v ev dd0 5.5 v ?1/f mck + 40 1/f mck + 40 ns sip hold time (from sckp ) note 2 t ksi2 1.8 v ev dd0 5.5 v 1/f mck + 31 1/f mck + 31 1/f mck + 31 ns 1.7 v ev dd0 5.5 v 1/f mck + 250 1/f mck + 250 1/f mck + 250 ns 1.6 v ev dd0 5.5 v ?1/f mck + 250 1/f mck + 250 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v ev dd0 5.5 v 2/f mck + 44 2/f mck + 110 2/f mck + 110 ns 2.4 v ev dd0 5.5 v 2/f mck + 75 2/f mck + 110 2/f mck + 110 ns 1.8 v ev dd0 5.5 v 2/f mck + 100 2/f mck + 110 2/f mck + 110 ns 1.7 v ev dd0 5.5 v 2/f mck + 220 2/f mck + 220 2/f mck + 220 ns 1.6 v ev dd0 5.5 v ?2/f mck + 220 2/f mck + 220 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 88 of 208 aug 12, 2016 remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0, 1, 3 to 5, 14) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13))
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 89 of 208 aug 12, 2016 caution select the normal input buffer for the sip pin and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remark p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim number (g = 3, 5) csi mode connection diagram (during communication at same potential) csi mode connection diagram (during communication at same potential) (slave transmission of slave se lect input function (csi00)) remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) (4) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. ssi00 setup time t ssik dapmn = 0 2.7 v ev dd0 5.5 v 120 120 120 ns 1.8 v ev dd0 5.5 v 200 200 200 ns 1.7 v ev dd0 5.5 v 400 400 400 ns 1.6 v ev dd0 5.5 v ? 400 400 ns dapmn = 1 2.7 v ev dd0 5.5 v 1/f mck + 120 1/f mck + 120 1/f mck + 120 ns 1.8 v ev dd0 5.5 v 1/f mck + 200 1/f mck + 200 1/f mck + 200 ns 1.7 v ev dd0 5.5 v 1/f mck + 400 1/f mck + 400 1/f mck + 400 ns 1.6 v ev dd0 5.5 v ?1/f mck + 400 1/f mck + 400 ns ssi00 hold time t kssi dapmn = 0 2.7 v ev dd0 5.5 v 1/f mck + 120 1/f mck + 120 1/f mck + 120 ns 1.8 v ev dd0 5.5 v 1/f mck + 200 1/f mck + 200 1/f mck + 200 ns 1.7 v ev dd0 5.5 v 1/f mck + 400 1/f mck + 400 1/f mck + 400 ns 1.6 v ev dd0 5.5 v ?1/f mck + 400 1/f mck + 400 ns dapmn = 1 2.7 v ev dd0 5.5 v 120 120 120 ns 1.8 v ev dd0 5.5 v 200 200 200 ns 1.7 v ev dd0 5.5 v 400 400 400 ns 1.6 v ev dd0 5.5 v ? 400 400 ns sckp sop user's device sck si sip so rl78 microcontroller sck00 so00 user's device sck si si00 so ssi00 sso rl78 microcontroller
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 90 of 208 aug 12, 2016 csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) sip sop t kcy1, 2 input data output data sckp t kl1, 2 t kh1, 2 ssi00 (csi00 only) t sik1, 2 t ksi1, 2 t kso1, 2 t ssik t kssi input data output data t kcy1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 t ssik t kssi sip sop sckp ssi00 (csi00 only) t kl1, 2
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 91 of 208 aug 12, 2016 ( notes and caution are listed on the next page, and remarks are listed on the page after the next page.) (5) during communication at sa me potential (simplified i 2 c mode) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sclr clock frequency f scl 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 1000 note 1 400 note 1 400 note 1 khz 1.8 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 400 note 1 400 note 1 400 note 1 khz 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 300 note 1 300 note 1 300 note 1 khz 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 250 note 1 250 note 1 250 note 1 khz 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 250 note 1 250 note 1 khz hold time when sclr = ?l? t low 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 475 1150 1150 ns 1.8 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 1150 1150 1150 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1550 1550 1550 ns 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1850 1850 1850 ns 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1850 1850 ns hold time when sclr = ?h? t high 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 475 1150 1150 ns 1.8 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 1150 1150 1150 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1550 1550 1550 ns 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1850 1850 1850 ns 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1850 1850 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 92 of 208 aug 12, 2016 note 1. the value must also be equal to or less than f mck /4. note 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the normal input buffer and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). ( remarks are listed on the next page.) (5) during communication at sa me potential (simplified i 2 c mode) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. data setup time (reception) t su: dat 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 1/f mck + 85 note 2 1/f mck + 145 note 2 1/f mck + 145 note 2 ns 1.8 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note 2 1/f mck + 145 note 2 1/f mck + 145 note 2 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1/f mck + 230 note 2 1/f mck + 230 note 2 1/f mck + 230 note 2 ns 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1/f mck + 290 note 2 1/f mck + 290 note 2 1/f mck + 290 note 2 ns 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1/f mck + 290 note 2 1/f mck + 290 note 2 ns data hold time (transmission) t hd: dat 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 030503050305ns 1.8 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 035503550355ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 040504050405ns 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 040504050405ns 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 0 405 0 405 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 93 of 208 aug 12, 2016 simplified i 2 c mode connection diagram (during communication at same potential) simplified i 2 c mode serial transfer timing (d uring communication at same potential) remark 1. r b [ ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance remark 2. r: iic number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: pim number (g = 0, 1, 3 to 5, 14), h: pom number (h = 0, 1, 3 to 5, 7, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) rl78 microcontroller sdar sclr user?s device sda scl v dd r b sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 94 of 208 aug 12, 2016 note 1. transfer rate in the snooze mode is 4800 bps only. however, the snooze mode cannot be used when frqsel4 = 1. note 2. use it with ev dd0 v b . note 3. the following conditions are required for low voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v: max. 2.6 mbps 1.8 v ev dd0 < 2.4 v: max. 1.3 mbps note 4. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (1.8 v v dd 5.5 v) lv (low-voltage main) mode: 4 mhz (1.6 v v dd 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13) remark 4. uart2 cannot communicate at different potential when bit 1 (pio r01) of peripheral i/o redire ction register 0 (pior0) is 1. (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. transfer rate reception 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v f mck /6 note 1 f mck /6 note 1 f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 4 5.3 1.3 0.6 mbps 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v f mck /6 note 1 f mck /6 note 1 f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 4 5.3 1.3 0.6 mbps 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v f mck /6 notes 1, 2, 3 f mck /6 notes 1, 2 f mck /6 notes 1, 2 bps theoretical value of the maximum transfer rate f mck = f clk note 4 5.3 1.3 0.6 mbps
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 95 of 208 aug 12, 2016 note 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v ev dd0 5.5 v and 2.7 v v b 4.0 v note 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum transfer rate under conditions of the customer. note 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ev dd0 < 4.0 v and 2.3 v v b 2.7 v (6) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. transfer rate transmission 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v note 1 note 1 note 1 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 2.8 note 2 2.8 note 2 mbps 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v note 3 note 3 note 3 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 1.2 note 4 1.2 note 4 mbps 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v notes 5, 6 notes 5, 6 notes 5, 6 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 7 0.43 note 7 0.43 note 7 mbps maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 2.2 v b {-c b r b in (1 - )} 2.2 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 2.0 v b {-c b r b in (1 - )} 2.0 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides .
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 96 of 208 aug 12, 2016 note 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. note 5. use it with ev dd0 v b . note 6. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 1.8 v ev dd0 < 3.3 v and 1.6 v v b 2.0 v note 7. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 6 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 1.5 v b {-c b r b in (1 - )} 1.5 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides .
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 97 of 208 aug 12, 2016 uart mode connection diagram (during communication at different potential) uart mode bit width (during communicatio n at different potential) (reference) remark 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) remark 4. uart2 cannot communicate at different potential when bit 1 (pio r01) of peripheral i/o redire ction register 0 (pior0) is 1. rl78 microcontroller txdq rxdq user?s device rx tx v b r b baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 98 of 208 aug 12, 2016 ( notes , caution , and remarks are listed on the next page.) (7) communication at different potential (2.5 v, 3 v) (csi mode) (mas ter mode, sckp... inte rnal clock output, corresponding csi00 only) (t a = -40 to +85c, 2.7 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 2/f clk 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 200 1150 1150 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 300 1150 1150 ns sckp high-level width t kh1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 - 50 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 - 120 t kcy1 /2 - 120 t kcy1 /2 - 120 ns sckp low-level width t kl1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k t kcy1 /2 - 7 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 - 10 t kcy1 /2 - 50 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 58 479 479 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 121 479 479 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 10 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 10 ns delay time from sckp to sop out- put note 1 t kso1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 60 60 60 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 130 130 130 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 99 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 3, 5) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) remark 4. this value is valid only w hen csi00?s peripheral i/o redirect function is not used. (7) communication at different potential (2.5 v, 3 v) (csi mode) (mas ter mode, sckp... inte rnal clock output, corresponding csi00 only) (t a = -40 to +85c, 2.7 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sip setup time (to sckp ) note 2 t sik1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 23 110 110 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 33 110 110 ns sip hold time (from sckp ) note 2 t ksi1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 10 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 10 ns delay time from sckp to sop output note 2 t kso1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 20 pf, r b = 1.4 k 10 10 10 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 10 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 100 of 208 aug 12, 2016 note use it with ev dd0 v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed two pages after the next page.) (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mo de, sckp... internal clock output) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 300 1150 1150 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 500 1150 1150 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note , c b = 30 pf, r b = 5.5 k 1150 1150 1150 ns sckp high-level width t kh1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 - 75 t kcy1 /2 - 75 t kcy1 /2 - 75 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 - 170 t kcy1 /2 - 170 t kcy1 /2 - 170 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note , c b = 30 pf, r b = 5.5 k t kcy1 /2 - 458 t kcy1 /2 - 458 t kcy1 /2 - 458 ns sckp low-level width t kl1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 - 12 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 - 18 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note , c b = 30 pf, r b = 5.5 k t kcy1 /2 - 50 t kcy1 /2 - 50 t kcy1 /2 - 50 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 101 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. use it with ev dd0 v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the page after the next page.) (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mo de, sckp... internal clock output) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/3) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sip setup time (to sckp ) note 1 t sik1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 81 479 479 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 479 479 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 479 479 479 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 19 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 19 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 19 19 19 ns delay time from sckp to sop output note 1 t kso1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 100 100 100 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 195 195 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 483 483 483 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 102 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. use it with ev dd0 v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) (8) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mo de, sckp... internal clock output) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (3/3) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sip setup time (to sckp ) note 1 t sik1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 44 110 110 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 110 110 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 110 110 110 ns sip hold time (from sckp ) note 1 t ksi1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 19 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 19 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 19 19 19 ns delay time from sckp to sop output note 1 t kso1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 25 25 25 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 25 25 25 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 25 25 25 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 103 of 208 aug 12, 2016 csi mode connection diagram (during communication at different potential remark 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) remark 4. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. sckp sop user?s device sck si sip so v b r b v b r b rl78 microcontroller
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 104 of 208 aug 12, 2016 csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 2. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. input data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 output data sckp input data output data sip sop sckp t kcy1 t kh1 t kl1 t sik1 t ksi1 t kso1
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 105 of 208 aug 12, 2016 ( notes , caution , and remarks are listed on the next page.) (9) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mo de) (slave mode, sckp... external clock input) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time note 1 t kcy2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v 24 mhz < f mck 14/f mck ??ns 20 mhz < f mck 24 mhz 12/f mck ??ns 8 mhz < f mck 20 mhz 10/f mck ??ns 4 mhz < f mck 8 mhz 8/f mck 16/f mck ?ns f mck 4 mhz 6/f mck 10/f mck 10/f mck ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v 24 mhz < f mck 20/f mck ??ns 20 mhz < f mck 24 mhz 16/f mck ??ns 16 mhz < f mck 20 mhz 14/f mck ??ns 8 mhz < f mck 16 mhz 12/f mck ??ns 4 mhz < f mck 8 mhz 8/f mck 16/f mck ?ns f mck 4 mhz 6/f mck 10/f mck 10/f mck ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 24 mhz < f mck 48/f mck ??ns 20 mhz < f mck 24 mhz 36/f mck ??ns 16 mhz < f mck 20 mhz 32/f mck ??ns 8 mhz < f mck 16 mhz 26/f mck ??ns 4 mhz < f mck 8 mhz 16/f mck 16/f mck ?ns f mck 4 mhz 10/f mck 10/f mck 10/f mck ns sckp high-/ low-level width t kh2 , t kl2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 - 12 t kcy2 /2 - 50 t kcy2 /2 - 50 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 - 18 t kcy2 /2 - 50 t kcy2 /2 - 50 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 t kcy2 /2 - 50 t kcy2 /2 - 50 t kcy2 /2 - 50 ns sip setup time (to sckp ) note 3 t sik2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 1/f mck + 30 1/f mck + 30 1/f mck + 30 ns sip hold time (from sckp ) note 4 t ksi2 1/f mck + 31 1/f mck + 31 1/f mck + 31 ns delay time from sckp to sop output note 5 t kso2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 120 2/f mck + 573 2/f mck + 573 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 214 2/f mck + 573 2/f mck + 573 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r v = 5.5 k 2/f mck + 573 2/f mck + 573 2/f mck + 573 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 106 of 208 aug 12, 2016 note 1. transfer rate in the snooze mode: max. 1 mbps note 2. use it with ev dd0 v b . note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and sckp pin, and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) remark 1. r b [ ]: communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13)) remark 4. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. also, communication at different potential cannot be perfo rmed during clock synchronous se rial communication with the slave select function. sckp sop user?s device sck si sip so v b r b rl78 microcontroller
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 107 of 208 aug 12, 2016 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 2. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. also, communication at different potential cannot be perfo rmed during clock synchronous se rial communication with the slave select function. sip sop sckp input data output data t kcy2 t kh2 t kl2 t sik2 t ksi2 t kso2 input data output data sip sop sckp t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 108 of 208 aug 12, 2016 (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sclr clock frequency f scl 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1000 note 1 300 note 1 300 note 1 khz 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1000 note 1 300 note 1 300 note 1 khz 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 400 note 1 300 note 1 300 note 1 khz 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 400 note 1 300 note 1 300 note 1 khz 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 300 note 1 300 note 1 300 note 1 khz hold time when sclr = ?l? t low 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 475 1550 1550 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 475 1550 1550 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1150 1550 1550 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1150 1550 1550 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 1550 1550 1550 ns hold time when sclr = ?h? t high 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 245 610 610 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 200 610 610 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 675 610 610 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 600 610 610 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 610 610 610 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 109 of 208 aug 12, 2016 note 1. the value must also be equal to or less than f mck /4. note 2. use it with ev dd0 v b . note 3. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sdar pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) (10) communication at different potential (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. data setup time (reception) t su:dat 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns data hold time (transmission) t hd:dat 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 0 305 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 0 305 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 355 0 355 0 355 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 355 0 355 0 355 ns 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 100 pf, r b = 5.5 k 0 405 0 405 0 405 ns
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 110 of 208 aug 12, 2016 simplified i 2 c mode connection diagram (during communication at different potential) simplified i 2 c mode serial transfer timing (durin g communication at different potential) remark 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage remark 2. r: iic number (r = 00, 01, 10, 11, 20, 30, 31), g: pim, pom number (g = 0, 1, 3 to 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 01, 02, 10, 12, 13) rl78 microcontroller sdar sclr user?s device sda scl v b r b v b r b sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 111 of 208 aug 12, 2016 2.5.2 serial interface iica ( notes , caution , and remark are listed on the next page.) (1) i 2 c standard mode (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. scla0 clock frequency f scl standard mode: f clk 1 mhz 2.7 v ev dd0 5.5 v 0 100 0 100 0 100 khz 1.8 v ev dd0 5.5 v 0 100 0 100 0 100 khz 1.7 v ev dd0 5.5 v 0 100 0 100 0 100 khz 1.6 v ev dd0 5.5 v ? 0 100 0 100 khz setup time of restart condition t su: sta 2.7 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.8 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.7 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.6 v ev dd0 5.5 v ? 4.7 4.7 s hold time note 1 t hd: sta 2.7 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.8 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.7 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.6 v ev dd0 5.5 v ? 4.0 4.0 s hold time when scla0 = ?l? t low 2.7 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.8 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.7 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.6 v ev dd0 5.5 v ? 4.7 4.7 s hold time when scla0 = ?h? t high 2.7 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.8 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.7 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.6 v ev dd0 5.5 v ? 4.0 4.0 s
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 112 of 208 aug 12, 2016 note 1. the first clock pulse is generated after this period when the start/restart condition is detected. note 2. the maximum value (max.) of t hd: dat is during normal transfer and a wait st ate is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bi t 2 (pior02) in the peripheral i/o redirection register 0 (pior0) is 1. at this time , the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k (1) i 2 c standard mode (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. data setup time (reception) t su: dat 2.7 v ev dd0 5.5 v 250 250 250 ns 1.8 v ev dd0 5.5 v 250 250 250 ns 1.7 v ev dd0 5.5 v 250 250 250 ns 1.6 v ev dd0 5.5 v ? 250 250 ns data hold time (transmission) note 2 t hd: dat 2.7 v ev dd0 5.5 v 0 3.45 0 3.45 0 3.45 s 1.8 v ev dd0 5.5 v 0 3.45 0 3.45 0 3.45 s 1.7 v ev dd0 5.5 v 0 3.45 0 3.45 0 3.45 s 1.6 v ev dd0 5.5 v ? 03.4503.45 s setup time of stop condition t su: sto 2.7 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.8 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.7 v ev dd0 5.5 v 4.0 4.0 4.0 s 1.6 v ev dd0 5.5 v ? 4.0 4.0 s bus-free time t buf 2.7 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.8 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.7 v ev dd0 5.5 v 4.7 4.7 4.7 s 1.6 v ev dd0 5.5 v ? 4.7 4.7 s
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 113 of 208 aug 12, 2016 note 1. the first clock pulse is generated after this period when the start/restart condition is detected. note 2. the maximum value (max.) of t hd: dat is during normal transfer and a wait st ate is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bi t 2 (pior02) in the peripheral i/o redirection register 0 (pior0) is 1. at this time , the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. fast mode: c b = 320 pf, r b = 1.1 k (2) i 2 c fast mode (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. scla0 clock frequency f scl fast mode: f clk 3.5 mhz 2.7 v ev dd0 5.5 v 0 400 0 400 0 400 khz 1.8 v ev dd0 5.5 v 0 400 0 400 0 400 khz setup time of restart condi- tion t su: sta 2.7 v ev dd0 5.5 v 0.6 0.6 0.6 s 1.8 v ev dd0 5.5 v 0.6 0.6 0.6 s hold time note 1 t hd: sta 2.7 v ev dd0 5.5 v 0.6 0.6 0.6 s 1.8 v ev dd0 5.5 v 0.6 0.6 0.6 s hold time when scla0 = ?l? t low 2.7 v ev dd0 5.5 v 1.3 1.3 1.3 s 1.8 v ev dd0 5.5 v 1.3 1.3 1.3 s hold time when scla0 = ?h? t high 2.7 v ev dd0 5.5 v 0.6 0.6 0.6 s 1.8 v ev dd0 5.5 v 0.6 0.6 0.6 s data setup time (reception) t su: dat 2.7 v ev dd0 5.5 v 100 100 100 ns 1.8 v ev dd0 5.5 v 100 100 100 ns data hold time (transmission) note 2 t hd: dat 2.7 v ev dd0 5.5 v 0 0.9 0 0.9 0 0.9 s 1.8 v ev dd0 5.5 v 0 0.9 0 0.9 0 0.9 s setup time of stop condition t su: sto 2.7 v ev dd0 5.5 v 0.6 0.6 0.6 s 1.8 v ev dd0 5.5 v 0.6 0.6 0.6 s bus-free time t buf 2.7 v ev dd0 5.5 v 1.3 1.3 1.3 s 1.8 v ev dd0 5.5 v 1.3 1.3 1.3 s
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 114 of 208 aug 12, 2016 note 1. the first clock pulse is generated after this period when the start/restart condition is detected. note 2. the maximum value (max.) of t hd: dat is during normal transfer and a wait st ate is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bi t 2 (pior02) in the peripheral i/o redirection register 0 (pior0) is 1. at this time , the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. note 3. the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. fast mode plus: c b = 120 pf, r b = 1.1 k iica serial transfer timing remark n = 0, 1 (3) i 2 c fast mode plus (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. scla0 clock frequency f scl fast mode plus: f clk 10 mhz 2.7 v ev dd0 5.5 v 0 1000 ? ? khz setup time of restart condi- tion t su: sta 2.7 v ev dd0 5.5 v 0.26 ? ? s hold time note 1 t hd: sta 2.7 v ev dd0 5.5 v 0.26 ? ? s hold time when scla0 = ?l? t low 2.7 v ev dd0 5.5 v 0.5 ? ? s hold time when scla0 = ?h? t high 2.7 v ev dd0 5.5 v 0.26 ? ? s data setup time (reception) t su: dat 2.7 v ev dd0 5.5 v 50 ? ? ns data hold time (transmission) note 2 t hd: dat 2.7 v ev dd0 5.5 v 0 0.45 ? ? s setup time of stop condition t su: sto 2.7 v ev dd0 5.5 v 0.26 ? ? s bus-free time t buf 2.7 v ev dd0 5.5 v 0.5 ? ? s t su: dat t hd: sta restart condition sclan sdaan t low t high t su: sta t hd: sta t su: sto stop condition stop condition start condition t hd: dat t buf
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 115 of 208 aug 12, 2016 2.6 analog characteristics 2.6.1 a/d converte r characteristics note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (%fsr) to the full-scale value. note 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . note 4. values when the conversion time is set to 57 s (min.) and 95 s (max.). note 5. refer to 2.6.2 temperature sensor characteristics/internal reference voltage characteristic . classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage (-) = av refm reference voltage (+) = v dd reference voltage (-) = v ss reference voltage (+) = v bgr reference voltage (-)= av refm ani0 to ani14 refer to 2.6.1 (1) .refer to 2.6.1 (3) . refer to 2.6.1 (4) . ani16 to ani20 refer to 2.6.1 (2) . internal reference voltage temperature sensor output voltage refer to 2.6.1 (1) .? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), ta rget pin: ani2 to ani14, internal referen ce voltage, and te mperature sensor output voltage (t a = -40 to +85c, 1.6 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 810bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.8 v av refp 5.5 v 1.2 3.5 lsb 1.6 v av refp 5.5 v note 4 1.2 7.0 lsb conversion time t conv 10-bit resolution target pin: ani2 to ani14 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 1.8 v v dd 5.5 v 17 39 s 1.6 v v dd 5.5 v 57 95 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 1.8 v av refp 5.5 v 0.25 %fsr 1.6 v av refp 5.5 v note 4 0.50 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 1.8 v av refp 5.5 v 0.25 %fsr 1.6 v av refp 5.5 v note 4 0.50 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 1.8 v av refp 5.5 v 2.5 lsb 1.6 v av refp 5.5 v note 4 5.0 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 1.8 v av refp 5.5 v 1.5 lsb 1.6 v av refp 5.5 v note 4 2.0 lsb analog input voltage v ain ani2 to ani14 0 av refp v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 5 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 5 v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 116 of 208 aug 12, 2016 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (%fsr) to the full-scale value. note 3. when ev dd0 av refp v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . note 4. when av refp < ev dd0 v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd . note 5. when the conversion time is set to 57 s (min.) and 95 s (max.). (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), target pin: ani16 to ani20 (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, 1.6 v av refp v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 810bit overall error note 1 ainl 10-bit resolution ev dd0 av refp = v dd notes 3, 4 1.8 v av refp 5.5 v 1.2 5.0 lsb 1.6 v av refp 5.5 v note 5 1.2 8.5 lsb conversion time t conv 10-bit resolution target ani pin: ani16 to ani20 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 1.8 v v dd 5.5 v 17 39 s 1.6 v v dd 5.5 v 57 95 s zero-scale error notes 1, 2 e zs 10-bit resolution ev dd0 av refp = v dd notes 3, 4 1.8 v av refp 5.5 v 0.35 %fsr 1.6 v av refp 5.5 v note 5 0.60 %fsr full-scale error notes 1, 2 e fs 10-bit resolution ev dd0 av refp = v dd notes 3, 4 1.8 v av refp 5.5 v 0.35 %fsr 1.6 v av refp 5.5 v note 5 0.60 %fsr integral linearity error note 1 ile 10-bit resolution ev dd0 av refp = v dd notes 3, 4 1.8 v av refp 5.5 v 3.5 lsb 1.6 v av refp 5.5 v note 5 6.0 lsb differential linearity error note 1 dle 10-bit resolution ev dd0 av refp = v dd notes 3, 4 1.8 v av refp 5.5 v 2.0 lsb 1.6 v av refp 5.5 v note 5 2.5 lsb analog input voltage v ain ani16 to ani20 0 av refp and ev dd0 v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 117 of 208 aug 12, 2016 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. note 3. when the conversion time is set to 57 s (min.) and 95 s (max.). note 4. refer to 2.6.2 temperature sensor characteristics/internal reference voltage characteristic . (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage (-) = v ss (adrefm = 0), target pin: ani0 to ani14, ani16 to ani20, internal reference voltage, an d temperature sensor output volt- age (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v dd , reference voltage (-) = v ss ) parameter symbol conditions min. typ. max. unit resolution res 810bit overall error note 1 ainl 10-bit resolution 1.8 v v dd 5.5 v 1.2 7.0 lsb 1.6 v v dd 5.5 v note 3 1.2 10.5 lsb conversion time t conv 10-bit resolution target pin: ani0 to ani14, ani16 to ani20 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 1.8 v v dd 5.5 v 17 39 s 1.6 v v dd 5.5 v 57 95 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 10-bit resolution 1.8 v v dd 5.5 v 0.60 %fsr 1.6 v v dd 5.5 v note 3 0.85 %fsr full-scale error notes 1, 2 e fs 10-bit resolution 1.8 v v dd 5.5 v 0.60 %fsr 1.6 v v dd 5.5 v note 3 0.85 %fsr integral linearity error note 1 ile 10-bit resolution 1.8 v v dd 5.5 v 4.0 lsb 1.6 v v dd 5.5 v note 3 6.5 lsb differential linearity error note 1 dle 10-bit resolution 1.8 v v dd 5.5 v 2.0 lsb 1.6 v v dd 5.5 v note 3 2.5 lsb analog input voltage v ain ani0 to ani14 0 v dd v ani16 to ani20 0 ev dd0 v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 4 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 118 of 208 aug 12, 2016 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. note 3. refer to 2.6.2 temperature sensor characteristics/internal reference voltage characteristic . note 4. when reference voltage (-) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage (-) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage (-) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage (-) = av refm . (4) when reference voltage (+) = intern al reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage (-) = av refm /ani1 (adrefm = 1), target pin: ani0, ani2 to ani14, ani16 to ani20 (t a = -40 to +85c, 2.4 v v dd 5.5 v, 1.6 v ev dd = ev dd1 v dd , v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v bgr note 3 , reference vo ltage (-) = av refm = 0 v note 4 , hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution res 8 bit conversion time t conv 8-bit resolution 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 8-bit resolution 2.4 v v dd 5.5 v 0.60 % fsr integral linearity error note 1 ile 8-bit resolution 2.4 v v dd 5.5 v 2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.4 v v dd 5.5 v 1.0 lsb analog input voltage v ain 0 v bgr note 3 v
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 119 of 208 aug 12, 2016 2.6.2 temperature sensor characteristics/internal reference voltage characteristic 2.6.3 d/a converter characteristics (t a = -40 to +85c, 2.4 v v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature -3.6 mv/ c operation stabilization wait time t amp 5 s (t a = -40 to +85c, 1.6 v ev ss0 = ev ss1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8bit overall error ainl rload = 4 m 1.8 v v dd 5.5 v 2.5 lsb rload = 8 m 1.8 v v dd 5.5 v 2.5 lsb settling time t set cload = 20 pf 2.7 v v dd 5.5 v 3 s 1.6 v v dd < 2.7 v 6 s
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 120 of 208 aug 12, 2016 2.6.4 comparator note not usable in ls (low-speed main) mode, lv (low-voltage main) mode, sub-clock operation, or stop mode. 2.6.5 por circui t characteristics note 1. however, when the operating voltage falls while the lvd is off, enter stop mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 2.4 ac characteristics. note 2. minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). (t a = -40 to +85c, 1.6 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit input voltage range ivref 0ev dd0 - 1.4 v ivcmp -0.3 ev dd0 + 0.3 v output delay td v dd = 3.0 v input slew rate > 50 mv/ s comparator high-speed mode, standard mode 1.2 s comparator high-speed mode, window mode 2.0 s comparator low-speed mode, standard mode 3.0 5.0 s high-electric-potential reference voltage vtw+ comparator high-speed mode, window mode 0.76 v dd v low-electric-potential ref- erence voltage vtw- comparator high-speed mode, window mode 0.24 v dd v operation stabilization wait time t cmp 100 s internal reference voltage note v bgr 2.4 v v dd 5.5 v, hs (high-speed main) mode 1.38 1.45 1.50 v (t a = -40 to +85c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power on/down reset threshold v por voltage threshold on v dd rising 1.47 1.51 1.55 v v pdr voltage threshold on v dd falling note 1 1.46 1.50 1.54 v minimum pulse width note 2 t pw 300 s t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 121 of 208 aug 12, 2016 2.6.6 lvd circui t characteristics (1) reset mode and interrupt mode (t a = -40 to +85c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit voltage detection threshold supply voltage level v lvd0 rising edge 3.98 4.06 4.14 v falling edge 3.90 3.98 4.06 v v lvd1 rising edge 3.68 3.75 3.82 v falling edge 3.60 3.67 3.74 v v lvd2 rising edge 3.07 3.13 3.19 v falling edge 3.00 3.06 3.12 v v lvd3 rising edge 2.96 3.02 3.08 v falling edge 2.90 2.96 3.02 v v lvd4 rising edge 2.86 2.92 2.97 v falling edge 2.80 2.86 2.91 v v lvd5 rising edge 2.76 2.81 2.87 v falling edge 2.70 2.75 2.81 v v lvd6 rising edge 2.66 2.71 2.76 v falling edge 2.60 2.65 2.70 v v lvd7 rising edge 2.56 2.61 2.66 v falling edge 2.50 2.55 2.60 v v lvd8 rising edge 2.45 2.50 2.55 v falling edge 2.40 2.45 2.50 v v lvd9 rising edge 2.05 2.09 2.13 v falling edge 2.00 2.04 2.08 v v lvd10 rising edge 1.94 1.98 2.02 v falling edge 1.90 1.94 1.98 v v lvd11 rising edge 1.84 1.88 1.91 v falling edge 1.80 1.84 1.87 v v lvd12 rising edge 1.74 1.77 1.81 v falling edge 1.70 1.73 1.77 v v lvd13 rising edge 1.64 1.67 1.70 v falling edge 1.60 1.63 1.66 v minimum pulse width t lw 300 s detection delay time 300 s
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 122 of 208 aug 12, 2016 2.6.7 power supply voltage rising slope characteristics caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 2.4 ac characteristics. (2) interrupt & reset mode (t a = -40 to +85c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit voltage detection threshold v lvda0 v poc2 , v poc1 , v poc0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 v v lvda1 lvis1, lvis0 = 1, 0 rising release reset voltage 1.74 1.77 1.81 v falling interrupt voltage 1.70 1.73 1.77 v v lvda2 lvis1, lvis0 = 0, 1 rising release reset voltage 1.84 1.88 1.91 v falling interrupt voltage 1.80 1.84 1.87 v v lvda3 lvis1, lvis0 = 0, 0 rising release reset voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvdb0 v poc2 , v poc1 , v poc0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 v v lvdb1 lvis1, lvis0 = 1, 0 rising release reset voltage 1.94 1.98 2.02 v falling interrupt voltage 1.90 1.94 1.98 v v lvdb2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.05 2.09 2.13 v falling interrupt voltage 2.00 2.04 2.08 v v lvdb3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.07 3.13 3.19 v falling interrupt voltage 3.00 3.06 3.12 v v lvdc0 v poc2 , v poc1 , v poc0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 v v lvdc1 lvis1, lvis0 = 1, 0 rising release reset voltage 2.56 2.61 2.66 v falling interrupt voltage 2.50 2.55 2.60 v v lvdc2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.66 2.71 2.76 v falling interrupt voltage 2.60 2.65 2.70 v v lvdc3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.68 3.75 3.82 v falling interrupt voltage 3.60 3.67 3.74 v v lvdd0 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 v v lvdd1 lvis1, lvis0 = 1, 0 rising release reset voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvdd2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.96 3.02 3.08 v falling interrupt voltage 2.90 2.96 3.02 v v lvdd3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.98 4.06 4.14 v falling interrupt voltage 3.90 3.98 4.06 v (t a = -40 to +85c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 123 of 208 aug 12, 2016 2.7 ram data retention characteristics note the value depends on the por detection voltage. when the volt age drops, the ram data is retained before a por reset is effected, but ram data is not retained when a por reset is effected. 2.8 flash memory programming characteristics note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. note 2. when using flash memory programmer and renes as electronics self-programming library note 3. these are the characteristics of the flash memory and the results obtained from reliability testing by renesas electronics corporation. 2.9 dedicated flash memory programmer communication (uart) (t a = -40 to +85c, v ss = 0v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 5.5 v (t a = -40 to +85c, 1.8 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit system clock frequency f clk 1.8 v v dd 5.5 v 1 32 mhz number of code flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85c 1,000 times number of data flash rewrites notes 1, 2, 3 retained for 1 year t a = 25c 1,000,000 retained for 5 years t a = 85c 100,000 retained for 20 years t a = 85c 10,000 (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps v dd stop instruction execution standby release signal (interrupt request) stop mode ram data retention operation mode v dddr
rl78/g14 2. electrical specifications (t a = -40 to +85 c) r01ds0053ej0330 rev. 3.30 page 124 of 208 aug 12, 2016 2.10 timing of entry to flash memory programming modes <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial comm unication settings within 100 ms from when the external resets end. t su : how long from when the tool0 pin is plac ed at the low level until a pin reset ends t hd: how long to keep the tool0 pin at the low level from when the external resets end (excluding the processing time of the fi rmware to control the flash memory) (t a = -40 to +85c, 1.8 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1ms reset tool0 <1> <2> <3> t su <4> t suinit 723 s + t hd processing time 00h reception (toolrxd, tooltxd mode)
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 125 of 208 aug 12, 2016 3. electrical specifications (g: industrial applications t a = -40 to +105 c) this chapter describes the following electrical specifications. target products g: industrial applications t a = -40 to +105c r5f104xxgxx caution 1. the rl78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. caution 2. with products not provided with an ev dd0 , ev dd1 , ev ss0 , or ev ss1 pin, replace ev dd0 and ev dd1 with v dd , or replace ev ss0 and ev ss1 with v ss . caution 3. the pins mounted depend on the product. refer to 2.1 port functions to 2.2.1 functions for each product in the rl78/g14 user?s manual. caution 4. please contact renesas electronics sale s office for derating of operation under t a = +85 to +105c. derating is the systematic reduction of load for the sake of improved reliability. remark when rl78/g14 is used in the range of t a = -40 to +85c, see 2. electrical specifications (t a = - 40 to +85c) .
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 126 of 208 aug 12, 2016 operation of products rated ?g : industrial applications (t a = -40 to + 105 c)? at ambient operating temperatures above 85 c differs from that of products rated ?a: consumer applications? and ?d: industrial applications? in the ways listed below. remark the electrical characteristics of produc ts rated ?g: industrial applications (t a = -40 to + 105c)? at ambient operating temperatures above 85c differ from those of products ra ted ?a: consumer applications? and ?d: industrial applications?. for details, refer to 3.1 to 3.10 . parameter a: consumer applications, d: indus trial applications g: i ndustrial applications operating ambient temperature t a = -40 to +85 ct a = -40 to +105 c operating mode operating voltage range hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd 5.5 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 5.5 v@1 mhz to 4 mhz hs (high-speed main) mode only: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz high-speed on-chip oscillator clock accuracy 1.8 v v dd 5.5 v: 1.0% @ t a = -20 to +85 c 1.5% @ t a = -40 to -20 c 1.6 v v dd < 1.8 v: 5.0% @ t a = -20 to +85 c 5.5% @ t a = -40 to -20 c 2.4 v v dd 5.5 v: 2.0% @ t a = +85 to +105 c 1.0% @ t a = -20 to +85 c 1.5% @ t a = -40 to -20 c serial array unit uart csi: f clk /2 (16 mbps supported), f clk /4 simplified i 2 c communication uart csi: f clk /4 simplified i 2 c communication iica standard mode fast mode fast mode plus standard mode fast mode voltage detector ? rising: 1.67 v to 4.06 v (14 stages) ? falling: 1.63 v to 3.98 v (14 stages) ? rising: 2.61 v to 4.06 v (8 stages) ? falling: 2.55 v to 3.98 v (8 stages)
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 127 of 208 aug 12, 2016 3.1 absolute maximum ratings note 1. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. note 2. must be 6.5 v or lower. note 3. do not exceed av ref (+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark 1. unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. remark 2. av ref (+): + side reference voltage of the a/d converter. remark 3. v ss : reference voltage absolute maximum ratings (1/2) parameter symbols conditions ratings unit supply voltage v dd -0.5 to +6.5 v ev dd0 , ev dd1 ev dd0 = ev dd1 -0.5 to +6.5 v ev ss0 , ev ss1 ev ss0 = ev ss1 -0.5 to +0.3 v regc pin input voltage v iregc regc -0.3 to +2.8 and -0.3 to v dd +0.3 note 1 v input voltage v i1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 -0.3 to ev dd0 +0.3 and -0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) -0.3 to +6.5 v v i3 p20 to p27, p121 to p124, p137, p150 to p156, exclk, exclks, reset -0.3 to v dd +0.3 note 2 v output voltage v o1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 -0.3 to ev dd0 +0.3 and -0.3 to v dd +0.3 note 2 v v o2 p20 to p27, p150 to p156 -0.3 to v dd +0.3 note 2 v analog input voltage v ai1 ani16 to ani20 -0.3 to ev dd0 +0.3 and -0.3 to av ref (+) +0.3 notes 2, 3 v v ai2 ani0 to ani14 -0.3 to v dd +0.3 and -0.3 to av ref (+) +0.3 notes 2, 3 v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 128 of 208 aug 12, 2016 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. absolute maximum ratings (2/2) parameter symbols conditions ratings unit output current, high i oh1 per pin p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 -40 ma total of all pins -170 ma p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 -70 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 -100 ma i oh2 per pin p20 to p27, p150 to p156 -0.5 ma total of all pins -2 ma output current, low i ol1 per pin p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 40 ma total of all pins 170 ma p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 70 ma p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 100 ma i ol2 per pin p20 to p27, p150 to p156 1 ma total of all pins 5ma operating ambient temperature t a in normal operation mode -40 to +105 c in flash memory programming mode storage temperature t stg -65 to +150 c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 129 of 208 aug 12, 2016 3.2 oscillator characteristics 3.2.1 x1, xt1 characteristics note indicates only permissible oscillat or frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscilla tor circuit mounted on a boa rd to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 oscillator and xt1 oscillator, refer to 5.4 system clock oscillator in the rl78/g14 user?s manual. 3.2.2 on-chip oscillator characteristics note 1. high-speed on-chip oscillator fr equency is selected with bits 0 to 4 of the option byte (000c2h) and bits 0 to 2 of the hocodiv register. note 2. this only indicates t he oscillator characte ristics. refer to ac characteristics for instruction execution time. (t a = -40 to +105c, 2.4 v v dd 5.5 v, v ss = 0 v) resonator resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 xt1 clock oscillation frequency (f xt ) note crystal resonator 32 32.768 35 khz (t a = -40 to +105c, 2.4 v v dd 5.5 v, v ss = 0 v) oscillators parameters co nditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 132mhz high-speed on-chip oscillator clock frequency accuracy -20 to +85c 2.4 v v dd 5.5 v -1.0 +1.0 % -40 to -20c 2.4 v v dd 5.5 v -1.5 +1.5 % +85 to +105c 2.4 v v dd 5.5 v -2.0 +2.0 % low-speed on-chip oscilla tor clock frequency f il 15 khz low-speed on-chip oscilla tor clock frequency accuracy -15 +15 %
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 130 of 208 aug 12, 2016 3.3 dc characteristics 3.3.1 pin characteristics note 1. value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , ev dd1 , v dd pins to an output pin. note 2. do not exceed the total current value. note 3. specification under conditi ons where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be ca lculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = -10.0 ma total output current of pins = (-10.0 0.7)/(80 0.01) -8.7 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00, p02 to p04, p10, p11, p13 to p15, p17, p30, p43 to p45, p50 to p55, p71, p74, p80 to p82, and p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 2.4 v ev dd0 5.5 v -3.0 note 2 ma total of p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v -30.0 ma 2.7 v ev dd0 < 4.0 v -10.0 ma 2.4 v ev dd0 < 2.7 v -5.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v -30.0 ma 2.7 v ev dd0 < 4.0 v -19.0 ma 2.4 v ev dd0 < 2.7 v -10.0 ma total of all pins (when duty 70% note 3 ) 2.4 v ev dd0 5.5 v -60.0 ma i oh2 per pin for p20 to p27, p150 to p156 2.4 v v dd 5.5 v -0.1 note 2 ma total of all pins (when duty 70% note 3 ) 2.4 v v dd 5.5 v -1.5 ma
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 131 of 208 aug 12, 2016 note 1. value of current at which the device operation is guarant eed even if the current flows from an output pin to the ev ss0 , ev ss1 , and v ss pins. note 2. do not exceed the total current value. note 3. specification under conditi ons where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can be ca lculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = 10.0 ma total output current of pins = (10.0 0.7)/(80 0.01) 8.7 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/5) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 8.5 note 2 ma per pin for p60 to p63 15.0 note 2 ma total of p00 to p04, p40 to p47, p102, p120, p130, p140 to p145 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v 40.0 ma 2.7 v ev dd0 < 4.0 v 15.0 ma 2.4 v ev dd0 < 2.7 v 9.0 ma total of p05, p06, p10 to p17, p30, p31, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p100, p101, p110, p111, p146, p147 (when duty 70% note 3 ) 4.0 v ev dd0 5.5 v 40.0 ma 2.7 v ev dd0 < 4.0 v 35.0 ma 2.4 v ev dd0 < 2.7 v 20.0 ma total of all pins (when duty 70% note 3 ) 80.0 ma i ol2 per pin for p20 to p27, p150 to p156 0.4 note 2 ma total of all pins (when duty 70% note 3 ) 2.4 v v dd 5.5 v 5.0 ma
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 132 of 208 aug 12, 2016 caution the maximum value of v ih of pins p00, p02 to p04, p10, p11, p13 to p15, p17, p30, p43 to p45, p50 to p55, p71, p74, p80 to p82, and p142 to p144 is ev dd0 , even in the n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (3/5) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 normal input buffer 0.8 ev dd0 ev dd0 v v ih2 p01, p03, p04, p10, p14 to p17, p30, p43, p44, p50, p53 to p55, p80, p81, p142, p143 ttl input buffer 4.0 v ev dd0 5.5 v 2.2 ev dd0 v ttl input buffer 3.3 v ev dd0 < 4.0 v 2.0 ev dd0 v ttl input buffer 2.4 v ev dd0 < 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p156 0.7 v dd v dd v v ih4 p60 to p63 0.7 ev dd0 6.0 v v ih5 p121 to p124, p137, exclk, exclks, reset 0.8 v dd v dd v input voltage, low v il1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 normal input buffer 0 0.2 ev dd0 v v il2 p01, p03, p04, p10, p14 to p17, p30, p43, p44, p50, p53 to p55, p80, p81, p142, p143 ttl input buffer 4.0 v ev dd0 5.5 v 00.8v ttl input buffer 3.3 v ev dd0 < 4.0 v 00.5v ttl input buffer 2.4 v ev dd0 < 3.3 v 00.32v v il3 p20 to p27, p150 to p156 0 0.3 v dd v v il4 p60 to p63 0 0.3 ev dd0 v v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2 v dd v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 133 of 208 aug 12, 2016 caution p00, p02 to p04, p10, p11, p13 to p15, p17, p30, p43 to p45, p50 to p55, p71, p74, p80 to p82, p142 to p144 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (4/5) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 4.0 v ev dd0 5.5 v, i oh1 = -3.0 ma ev dd0 - 0.7 v 2.7 v ev dd0 5.5 v, i oh1 = -2.0 ma ev dd0 - 0.6 v 2.4 v ev dd0 5.5 v, i oh1 = -1.5 ma ev dd0 - 0.5 v v oh2 p20 to p27, p150 to p156 2.4 v v dd 5.5 v, i oh2 = -100 a v dd - 0.5 v output voltage, low v ol1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p130, p140 to p147 4.0 v ev dd0 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v ev dd0 5.5 v, i ol1 = 3.0 ma 0.6 v 2.7 v ev dd0 5.5 v, i ol1 = 1.5 ma 0.4 v 2.4 v ev dd0 5.5 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p27, p150 to p156 2.4 v v dd 5.5 v, i ol2 = 400 a 0.4 v v ol3 p60 to p63 4.0 v ev dd0 5.5 v, i ol3 = 15.0 ma 2.0 v 4.0 v ev dd0 5.5 v, i ol3 = 5.0 ma 0.4 v 2.7 v ev dd0 5.5 v, i ol3 = 3.0 ma 0.4 v 2.4 v ev dd0 5.5 v, i ol3 = 2.0 ma 0.4 v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 134 of 208 aug 12, 2016 remark unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (5/5) items symbol conditions min. typ. max. unit input leakage cur- rent, high i lih1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 v i = ev dd0 1 a i lih2 p20 to p27, p137, p150 to p156, reset v i = v dd 1 a i lih3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v dd in input port or external clock input 1 a in resonator con- nection 10 a input leakage current, low i lil1 p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 v i = ev ss0 -1 a i lil2 p20 to p27, p137, p150 to p156, reset v i = v ss -1 a i lil3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v ss in input port or external clock input -1 a in resonator con- nection -10 a on-chip pull-up resistance r u p00 to p06, p10 to p17, p30, p31, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p87, p100 to p102, p110, p111, p120, p140 to p147 v i = ev ss0 , in input port 10 20 100 k
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 135 of 208 aug 12, 2016 3.3.2 supply current characteristics ( notes and remarks are listed on the next page.) (1) flash rom: 16 to 64 kb of 30- to 64-pin products (t a = -40 to +105c, 2.4 v ev dd0 v dd 5.5 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operat- ing mode hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.4 ma v dd = 3.0 v 2.4 f hoco = 32 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.1 v dd = 3.0 v 2.1 hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.1 9.3 ma v dd = 3.0 v 5.1 9.3 f hoco = 32 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 4.8 8.7 v dd = 3.0 v 4.8 8.7 f hoco = 48 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.0 7.3 v dd = 3.0 v 4.0 7.3 f hoco = 24 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 3.8 6.7 v dd = 3.0 v 3.8 6.7 f hoco = 16 mhz, f ih = 16 mhz note 3 normal operation v dd = 5.0 v 2.8 4.9 v dd = 3.0 v 2.8 4.9 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.3 5.7 ma resonator connection 3.4 5.8 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.3 5.7 resonator connection 3.4 5.8 f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 2.0 3.4 resonator connection 2.1 3.5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.0 3.4 resonator connection 2.1 3.5 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 4.7 6.1 a resonator connection 4.7 6.1 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 4.7 6.1 resonator connection 4.7 6.1 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 4.8 6.7 resonator connection 4.8 6.7 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 4.8 7.5 resonator connection 4.8 7.5 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 5.4 8.9 resonator connection 5.4 8.9 f sub = 32.768 khz note 4 t a = +105c normal operation square wave input 7.2 21.0 resonator connection 7.3 21.1
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 136 of 208 aug 12, 2016 note 1. total current flowing into v dd and ev dd0 , including the input leakage current flow ing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d conv erter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current flowing into the rtc, 12-bit interval timer, and watchdog timer. note 5. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 137 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (1) flash rom: 16 to 64 kb of 30- to 64-pin products (t a = -40 to +105c, 2.4 v ev dd0 v dd 5.5 v, v ss = ev ss0 = 0 v)(2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 64 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.80 4.36 ma v dd = 3.0 v 0.80 4.36 f hoco = 32 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.49 3.67 v dd = 3.0 v 0.49 3.67 f hoco = 48 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.62 3.42 v dd = 3.0 v 0.62 3.42 f hoco = 24 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.4 2.85 v dd = 3.0 v 0.4 2.85 f hoco = 16 mhz, f ih = 16 mhz note 4 v dd = 5.0 v 0.37 2.08 v dd = 3.0 v 0.37 2.08 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.28 2.45 ma resonator connection 0.40 2.57 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.28 2.45 resonator connection 0.40 2.57 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.19 1.28 resonator connection 0.25 1.36 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.19 1.28 resonator connection 0.25 1.36 subsystem clock operation f sub = 32.768 khz note 5 , t a = -40c square wave input 0.25 0.57 a resonator connection 0.44 0.76 f sub = 32.768 khz note 5 , t a = +25c square wave input 0.30 0.57 resonator connection 0.49 0.76 f sub = 32.768 khz note 5 , t a = +50c square wave input 0.36 1.17 resonator connection 0.59 1.36 f sub = 32.768 khz note 5 , t a = +70c square wave input 0.49 1.97 resonator connection 0.72 2.16 f sub = 32.768 khz note 5 , t a = +85c square wave input 0.97 3.37 resonator connection 1.16 3.56 f sub = 32.768 khz note 5 , t a = +105c square wave input 3.20 17.10 resonator connection 3.40 17.50 i dd3 note 6 stop mode note 8 t a = -40c 0.18 0.51 a t a = +25c 0.24 0.51 t a = +50c 0.29 1.10 t a = +70c 0.41 1.90 t a = +85c 0.90 3.30 t a = +105c 3.10 17.00
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 138 of 208 aug 12, 2016 note 1. total current flowing into v dd and ev dd0 , including the input leakage current flow ing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d conv erter, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit inte rval timer and watchdog timer. note 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 139 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operat- ing mode hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.6 ma v dd = 3.0 v 2.6 f hoco = 32 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.3 v dd = 3.0 v 2.3 hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.4 10.9 ma v dd = 3.0 v 5.4 10.9 f hoco = 32 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.0 10.3 v dd = 3.0 v 5.0 10.3 f hoco = 48 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.2 8.2 v dd = 3.0 v 4.2 8.2 f hoco = 24 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.0 7.8 v dd = 3.0 v 4.0 7.8 f hoco = 16 mhz, f ih = 16 mhz note 3 normal operation v dd = 5.0 v 3.0 5.6 v dd = 3.0 v 3.0 5.6 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.4 6.6 ma resonator connection 3.6 6.7 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.4 6.6 resonator connection 3.6 6.7 f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 2.1 3.9 resonator connection 2.2 4.0 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.1 3.9 resonator connection 2.2 4.0 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 4.9 7.1 a resonator connection 4.9 7.1 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 4.9 7.1 resonator connection 4.9 7.1 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 5.1 8.8 resonator connection 5.1 8.8 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 5.5 10.5 resonator connection 5.5 10.5 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 6.5 14.5 resonator connection 6.5 14.5 f sub = 32.768 khz note 4 t a = +105c normal operation square wave input 13.0 58.0 resonator connection 13.0 58.0
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 140 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/ d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillat ion). however, not including the current flowing into the 12-bit interval timer and watchdog timer. note 5. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 141 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (2) flash rom: 96 to 256 kb of 30- to 100-pin products (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply cur- rent note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 64 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.79 4.86 ma v dd = 3.0 v 0.79 4.86 f hoco = 32 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.49 4.17 v dd = 3.0 v 0.49 4.17 f hoco = 48 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.62 3.82 v dd = 3.0 v 0.62 3.82 f hoco = 24 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.4 3.25 v dd = 3.0 v 0.4 3.25 f hoco = 16 mhz, f ih = 16 mhz note 4 v dd = 5.0 v 0.38 2.28 v dd = 3.0 v 0.38 2.28 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.30 2.65 ma resonator connection 0.40 2.77 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.30 2.65 resonator connection 0.40 2.77 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.20 1.36 resonator connection 0.25 1.46 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.20 1.36 resonator connection 0.25 1.46 subsystem clock oper- ation f sub = 32.768 khz note 5 , t a = -40c square wave input 0.28 0.66 a resonator connection 0.47 0.85 f sub = 32.768 khz note 5 , t a = +25c square wave input 0.34 0.66 resonator connection 0.53 0.85 f sub = 32.768 khz note 5 , t a = +50c square wave input 0.37 2.35 resonator connection 0.56 2.54 f sub = 32.768 khz note 5 , t a = +70c square wave input 0.61 4.08 resonator connection 0.80 4.27 f sub = 32.768 khz note 5 , t a = +85c square wave input 1.55 8.09 resonator connection 1.74 8.28 f sub = 32.768 khz note 5 , t a = +105c square wave input 6.00 51.00 resonator connection 6.00 51.00 i dd3 note 6 stop mode note 8 t a = -40c 0.19 0.57 a t a = +25c 0.25 0.57 t a = +50c 0.33 2.26 t a = +70c 0.52 3.99 t a = +85c 1.46 8.00 t a = +105c 5.50 50.00
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 142 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/ d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit inte rval timer and watchdog timer. note 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 143 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (3) flash rom: 384 to 512 kb of 48- to 100-pin products (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operat- ing mode hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.9 ma v dd = 3.0 v 2.9 f hoco = 32 mhz, f ih = 32 mhz note 3 basic operation v dd = 5.0 v 2.5 v dd = 3.0 v 2.5 hs (high-speed main) mode note 5 f hoco = 64 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 6.0 11.2 ma v dd = 3.0 v 6.0 11.2 f hoco = 32 mhz, f ih = 32 mhz note 3 normal operation v dd = 5.0 v 5.5 10.6 v dd = 3.0 v 5.5 10.6 f hoco = 48 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.7 8.6 v dd = 3.0 v 4.7 8.6 f hoco = 24 mhz, f ih = 24 mhz note 3 normal operation v dd = 5.0 v 4.4 8.2 v dd = 3.0 v 4.4 8.2 f hoco = 16 mhz, f ih = 16 mhz note 3 normal operation v dd = 5.0 v 3.3 5.9 v dd = 3.0 v 3.3 5.9 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 5.0 v normal operation square wave input 3.7 6.8 ma resonator connection 3.9 7.0 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.7 6.8 resonator connection 3.9 7.0 f mx = 10 mhz note 2 , v dd = 5.0 v normal operation square wave input 2.3 4.1 resonator connection 2.3 4.2 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.3 4.1 resonator connection 2.3 4.2 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 5.2 7.7 a resonator connection 5.2 7.7 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 5.3 7.7 resonator connection 5.3 7.7 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 5.5 10.6 resonator connection 5.5 10.6 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 5.9 13.2 resonator connection 6.0 13.2 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 6.8 17.5 resonator connection 6.9 17.5 f sub = 32.768 khz note 4 t a = +105c normal operation square wave input 15.5 77.8 resonator connection 15.5 77.8
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 144 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/ d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillat ion). however, not including the current flowing into the 12-bit interval timer and watchdog timer. note 5. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 145 of 208 aug 12, 2016 ( notes and remarks are listed on the next page.) (3) flash rom: 384 to 512 kb of 48- to 100-pin products (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply cur- rent note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 64 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.93 5.16 ma v dd = 3.0 v 0.93 5.16 f hoco = 32 mhz, f ih = 32 mhz note 4 v dd = 5.0 v 0.5 4.47 v dd = 3.0 v 0.5 4.47 f hoco = 48 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.72 4.08 v dd = 3.0 v 0.72 4.08 f hoco = 24 mhz, f ih = 24 mhz note 4 v dd = 5.0 v 0.42 3.51 v dd = 3.0 v 0.42 3.51 f hoco = 16 mhz, f ih = 16 mhz note 4 v dd = 5.0 v 0.39 2.38 v dd = 3.0 v 0.39 2.38 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 5.0 v square wave input 0.31 2.83 ma resonator connection 0.41 2.92 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.31 2.83 resonator connection 0.41 2.92 f mx = 10 mhz note 3 , v dd = 5.0 v square wave input 0.21 1.46 resonator connection 0.26 1.57 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.21 1.46 resonator connection 0.26 1.57 subsystem clock oper- ation f sub = 32.768 khz note 5 , t a = -40c square wave input 0.31 0.76 a resonator connection 0.50 0.95 f sub = 32.768 khz note 5 , t a = +25c square wave input 0.38 0.76 resonator connection 0.57 0.95 f sub = 32.768 khz note 5 , t a = +50c square wave input 0.47 3.59 resonator connection 0.70 3.78 f sub = 32.768 khz note 5 , t a = +70c square wave input 0.80 6.20 resonator connection 1.00 6.39 f sub = 32.768 khz note 5 , t a = +85c square wave input 1.65 10.56 resonator connection 1.84 10.75 f sub = 32.768 khz note 5 , t a = +105c square wave input 8.00 65.7 resonator connection 8.00 65.7 i dd3 note 6 stop mode note 8 t a = -40c 0.19 0.63 a t a = +25c 0.30 0.63 t a = +50c 0.41 3.47 t a = +70c 0.80 6.08 t a = +85c 1.53 10.44 t a = +105c 6.50 67.14
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 146 of 208 aug 12, 2016 note 1. total current flowing into v dd , ev dd0 , and ev dd1 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 , and ev dd1 , or v ss , ev ss0 , and ev ss1 . the values below the ma x. column include the peripheral operation current. however, not including the current flowing into the a/ d converter, d/a converter, comparator, lvd circuit, i/o port, and on-chip pull-up/pull-down resistors and the current flow ing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit inte rval timer and watchdog timer. note 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operati on frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz 2.4 v v dd 5.5 v@1 mhz to 16 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (64 mhz max.) remark 3. f ih : high-speed on-chip oscillator clock frequency (32 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 147 of 208 aug 12, 2016 note 1. current flowing to v dd . note 2. when high speed on-chip oscillator and high-speed system clock are stopped. note 3. current flowing only to the real-time cl ock (rtc) (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or ha lt mode. when th e low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation in cludes the operational current of the real-time clock. note 4. current flowing only to the 12-bit interv al timer (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. (4) peripheral functions (common to all products) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit low-speed on-chip oscilla- tor operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operat- ing current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating cur- rent i adc notes 1, 6 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref note 1 75.0 a temperature sensor operat- ing current i tmps note 1 75.0 a d/a converter operating cur- rent i dac notes 1, 11, 13 per d/a converter channel 1.5 ma comparator operating cur- rent i cmp notes 1, 12, 13 v dd = 5.0 v, regulator output voltage = 2.1 v window mode 12.5 a comparator high-speed mode 6.5 a comparator low-speed mode 1.7 a v dd = 5.0 v, regulator output voltage = 1.8 v window mode 8.0 a comparator high-speed mode 4.0 a comparator low-speed mode 1.3 a lvd operating current i lvd notes 1, 7 0.08 a self-programming operat- ing current i fsp notes 1, 9 2.50 12.20 ma bgo operating current i bgo notes 1, 8 2.50 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 10 0.50 1.10 ma the a/d conversion opera- tions are performed, low volt- age mode, av refp = v dd = 3.0 v 1.20 2.04 csi/uart operation 0.70 1.54 dtc operation 3.10
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 148 of 208 aug 12, 2016 note 5. current flowing only to the watchdog timer (including th e operating current of the low-speed on-chip oscillator). the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer is in operation. note 6. current flowing only to the a/d conver ter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. note 7. current flowing only to the lvd circuit. the supply curre nt of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. note 8. current flowing during programming of the data flash. note 9. current flowing during self-programming. note 10. for shift time to the snooze mode, see 23.3.3 snooze mode in the rl78/g14 user?s manual. note 11. current flowing only to the d/a conver ter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i dac when the d/a converter operates in an operation mode or the halt mode. note 12. current flowing only to the comparator circuit. the supply current of the r l78 microcontrollers is the sum of i dd1 , i dd2 , or i dd3 and i cmp when the comparator circuit is in operation. note 13. a comparator and d/a converter are provided in products with 96 kb or more code flash memory. remark 1. f il : low-speed on-chip oscillator clock frequency remark 2. f sub : subsystem clock frequency (x t1 clock oscillation frequency) remark 3. f clk : cpu/peripheral hardware clock frequency remark 4. temperature condition of the typ. value is t a = 25c
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 149 of 208 aug 12, 2016 3.4 ac characteristics note the following conditions are required for low voltage interface when ev dd0 < v dd 2.4 v ev dd0 < 2.7 v: min. 125 ns remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn bit of timer mode regi ster mn (tmrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3)) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) items symbol conditions min. typ. max. unit instruction cycle (min- imum instruction exe- cution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v v dd 5.5 v 0.03125 1 s 2.4 v v dd < 2.7 v 0.0625 1 s subsystem clock (f sub ) operation 2.4 v v dd 5.5 v 28.5 30.5 31.3 s in the self- program- ming mode hs (high-speed main) mode 2.7 v v dd 5.5 v 0.03125 1 s 2.4 v v dd < 2.7 v 0.0625 1 s external system clock frequency f ex 2.7 v v dd 5.5 v 1.0 20.0 mhz 2.4 v v dd 2.7 v 1.0 16.0 mhz f exs 32 35 khz external system clock input high-level width, low-level width t exh , t exl 2.7 v v dd 5.5 v 24 ns 2.4 v v dd 2.7 v 30 ns t exhs , t exls 13.7 s ti00 to ti03, ti10 to ti13 input high-level width, low-level width t tih , t til 1/f mck + 10 note ns timer rj input cycle f c trjio 2.7 v ev dd0 5.5 v 100 ns 2.4 v ev dd0 < 2.7 v 300 ns timer rj input high- level width, low-level width t tjih , t tjil trjio 2.7 v ev dd0 5.5 v 40 ns 2.4 v ev dd0 < 2.7 v 120 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 150 of 208 aug 12, 2016 (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) items symbol conditions min. typ. max. unit timer rd input high-level width, low-level width t tdih , t tdil trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 3/f clk ns timer rd forced cutoff signal input low-level width t tdsil p130/intp0 2mhz < f clk 32 mhz 1 s f clk 2 mhz 1/f clk + 1 timer rg input high-level width, low-level width t tgih , t tgil trgioa, trgiob 2.5/f clk ns to00 to to03, to10 to to13, trjio0, trjo0, trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1, trgioa, trgiob output frequency f to hs (high-speed main) mode 4.0 v ev dd0 5.5 v 16 mhz 2.7 v ev dd0 < 4.0 v 8 mhz 2.4 v ev dd0 < 2.7 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 4.0 v ev dd0 5.5 v 16 mhz 2.7 v ev dd0 < 4.0 v 8 mhz 2.4 v ev dd0 < 2.7 v 4 mhz interrupt input high-level width, low-level width t inth , t intl intp0 2.4 v v dd 5.5 v 1 s intp1 to intp11 2.4 v ev dd0 5.5 v 1 s key interrupt input low-level width t kr kr0 to kr7 2.4 v ev dd0 5.5 v 250 ns reset low-level width t rsl 10 s
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 151 of 208 aug 12, 2016 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.03125 0.0625 0.05 cycle time t cy [s] supply voltage v dd [v] during self-programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 152 of 208 aug 12, 2016 ac timing test points external system clock timing ti/to timing v ih /v oh v il /v ol v ih /v oh test points v il /v ol exclk/exclks 1/f ex 1/f exs t exl t exls t exh t exhs t til t tih 1/f to ti00 to ti03, ti10 to ti13 to00 to to03, to10 to to13, trjio0, trjo0, trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1, trgioa, trgiob
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 153 of 208 aug 12, 2016 t tjil trjio t tjih t tdil trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 t tdih t tdsil intp0 t tgil trgioa, trgiob t tgih
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 154 of 208 aug 12, 2016 interrupt request input timing key interrupt input timing reset input timing intp0 to intp11 t intl t inth t kr kr0 to kr7 t rsl reset
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 155 of 208 aug 12, 2016 3.5 peripheral functions characteristics ac timing test points 3.5.1 serial array unit note 1. transfer rate in the snooze mode is 4800 bps only. however, the snooze mode cannot be used when frqsel4 = 1. note 2. the following conditions are required for low voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v: max. 1.3 mbps note 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (durin g communication at same potential) uart mode bit width (durin g communication at same potential) (reference) remark 1. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 5, 14) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (1) during communication at same potential (uart mode) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate note 1 2.4 v ev dd0 5.5 v f mck /12 note 2 bps theoretical value of t he maximum transfer rate f mck = f clk note 3 2.6 mbps v ih /v oh v il /v ol v ih /v oh test points v il /v ol rl78 microcontroller txdq rxdq user?s device rx tx baud rate error tolerance txdq rxdq high-/low-bit width 1/transfer rate
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 156 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0, 1, 3 to 5, 14) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (2) during communication at same potential (csi mo de) (master mode, sckp... internal clock output) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v e vdd0 5.5 v 250 ns 2.4 v ev dd0 5.5 v 500 ns sckp high-/low-level width t kh1 , t kl1 4.0 v ev dd0 5.5 v t kcy1 /2 - 24 ns 2.7 v ev dd0 5.5 v t kcy1 /2 - 36 ns 2.4 v ev dd0 5.5 v t kcy1 /2 - 76 ns sip setup time (to sckp ) note 1 t sik1 4.0 v ev dd0 5.5 v 66 ns 2.7 v ev dd0 5.5 v 66 ns 2.4 v ev dd0 5.5 v 113 ns sip hold time (from sckp ) note 2 t ksi1 38 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 50 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 157 of 208 aug 12, 2016 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sop output lines. note 5. the maximum transfer rate when using the snooze mode is 1 mbps. caution select the normal input buffer for the sip pin and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0, 1, 3 to 5, 14) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (3) during communication at same potential (csi mode) (slave mode , sckp... external clock input) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time note 5 t kcy2 4.0 v ev dd0 5.5 v 20 mhz < f mck 16/f mck ns f mck 20 mhz 12/f mck ns 2.7 v ev dd0 5.5 v 16 mhz < f mck 16/f mck ns f mck 16 mhz 12/f mck ns 2.4 v ev dd0 5.5 v 12/f mck and 1000 ns sckp high-/low-level width t kh2 , t kl2 4.0 v ev dd0 5.5 v t kcy2 /2 - 14 ns 2.7 v ev dd0 5.5 v t kcy2 /2 - 16 ns 2.4 v ev dd0 5.5 v t kcy2 /2 - 36 ns sip setup time (to sckp ) note 1 t sik2 2.7 v ev dd0 5.5 v 1/f mck + 40 ns 2.4 v ev dd0 5.5 v 1/f mck + 60 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck + 62 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v ev dd0 5.5 v 2/f mck + 66 ns 2.4 v ev dd0 5.5 v 2/f mck + 113 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 158 of 208 aug 12, 2016 caution select the normal input buffer for the sip pin and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remark p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim number (g = 3, 5) csi mode connection diagram (during communication at same potential) csi mode connection diagram (during communication at same potential) (slave transmission of slave se lect input function (csi00)) remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) (3) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode unit min. max. ssi00 setup time t ssik dapmn = 0 2.7 v ev dd0 5.5 v 240 ns 2.4 v ev dd0 5.5 v 400 ns dapmn = 1 2.7 v ev dd0 5.5 v 1/f mck + 240 ns 2.4 v ev dd0 5.5 v 1/f mck + 400 ns ssi00 hold time t kssi dapmn = 0 2.7 v ev dd0 5.5 v 1/f mck + 240 ns 2.4 v ev dd0 5.5 v 1/f mck + 400 ns dapmn = 1 2.7 v ev dd0 5.5 v 240 ns 2.4 v ev dd0 5.5 v 400 ns sckp sop user's device sck si sip so rl78 microcontroller sck00 so00 user's device sck si si00 so ssi00 sso rl78 microcontroller
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 159 of 208 aug 12, 2016 csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 01, 10, 11, 20, 21, 30, 31) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) sip sop t kcy1, 2 input data output data sckp t kl1, 2 t kh1, 2 ssi00 (csi00 only) t sik1, 2 t ksi1, 2 t kso1, 2 t ssik t kssi input data output data t kcy1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 t ssik t kssi sip sop sckp ssi00 (csi00 only) t kl1, 2
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 160 of 208 aug 12, 2016 note 1. the value must also be equal to or less than f mck /4. note 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the normal input buffer and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). ( remarks are listed on the next page.) (4) during communication at sa me potential (simplified i 2 c mode) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sclr clock frequency f scl 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 2.4 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 100 note 1 khz hold time when sclr = ?l? t low 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.4v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 4600 ns hold time when sclr = ?h? t high 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.4 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 4600 ns data setup time (reception) t su: dat 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 1/f mck + 220 note 2 ns 2.4v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 580 note 2 ns data hold time (transmission) t hd: dat 2.7 v ev dd0 5.5 v, c b = 50 pf, r b = 2.7 k 0 770 ns 2.4 v ev dd0 5.5 v, c b = 100 pf, r b = 3 k 0 1420 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 161 of 208 aug 12, 2016 simplified i 2 c mode connection diagram (during communication at same potential) simplified i 2 c mode serial transfer timing (d uring communication at same potential) remark 1. r b [ ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance remark 2. r: iic number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: pim number (g = 0, 1, 3 to 5, 14), h: pom number (h = 0, 1, 3 to 5, 7, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) rl78 microcontroller sdar sclr user?s device sda scl v dd r b sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 162 of 208 aug 12, 2016 note 1. transfer rate in the snooze mode is 4800 bps only. however, the snooze mode cannot be used when frqsel4 = 1. note 2. the following conditions are required for low voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v: max. 1.3 mbps note 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v v dd 5.5 v) 16 mhz (2.4 v v dd 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13) remark 4. uart2 cannot communicate at different potential when bit 1 (pio r01) of peripheral i/o redire ction register 0 (pior0) is 1. (5) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate reception 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 3 2.6 mbps 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 3 2.6 mbps 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v f mck /12 notes 1, 2 bps theoretical value of the maximum transfer rate f mck = f clk note 3 2.6 mbps
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 163 of 208 aug 12, 2016 note 1. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v ev dd0 5.5 v and 2.7 v v b 4.0 v note 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum transfer rate under conditions of the customer. note 3. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ev dd0 < 4.0 v and 2.3 v v b 2.7 v note 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum transfer rate under conditions of the customer. (5) communication at different potential (1.8 v, 2.5 v, 3 v) (uart mode) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate transmission 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v note 1 bps theoretical value of th e maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.6 note 2 mbps 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v note 3 bps theoretical value of th e maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 bps theoretical value of th e maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 6 mbps maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 2.2 v b {-c b r b in (1 - )} 2.2 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 2.0 v b {-c b r b in (1 - )} 2.0 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides .
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 164 of 208 aug 12, 2016 note 5. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v ev dd0 < 3.3 v and 1.6 v v b 2.0 v note 6. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 5 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate 2 - {-c b r b in (1 - )} 3 1.5 v b {-c b r b in (1 - )} 1.5 v b ( ) number of transferred bits 1 transfer rate 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides .
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 165 of 208 aug 12, 2016 uart mode connection diagram (during communication at different potential) uart mode bit width (during communicatio n at different potential) (reference) remark 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0, 1, 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) remark 4. uart2 cannot communicate at different potential when bit 1 (pio r01) of peripheral i/o redire ction register 0 (pior0) is 1. rl78 microcontroller txdq rxdq user?s device rx tx v b r b baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 166 of 208 aug 12, 2016 caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed two pages after the next page.) (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mo de, sckp... internal clock output) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time t kcy1 t kcy1 4/f clk 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 600 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 1000 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 2300 ns sckp high-level width t kh1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 - 150 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 - 340 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 - 916 ns sckp low-level width t kl1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 - 24 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 - 36 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 - 100 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 167 of 208 aug 12, 2016 note when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the page after the next page.) (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mo de, sckp... internal clock output) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/3) parameter symbol conditions hs (high-speed main) mode unit min. max. sip setup time (to sckp ) note t sik1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 162 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 354 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 958 ns sip hold time (from sckp ) note t ksi1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 38 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 38 ns delay time from sckp to sop output note t kso1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 200 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 390 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 966 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 168 of 208 aug 12, 2016 note when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) (6) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mode) (master mo de, sckp... internal clock output) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (3/3) parameter symbol conditions hs (high-speed main) mode unit min. max. sip setup time (to sckp ) note t sik1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 88 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 88 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 220 ns sip hold time (from sckp ) note t ksi1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 38 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 38 ns delay time from sckp to sop output note t kso1 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 50 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 50 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 50 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 169 of 208 aug 12, 2016 csi mode connection diagram (during communication at different potential remark 5. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 6. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 7. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) remark 8. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. sckp sop user?s device sck si sip so v b r b v b r b rl78 microcontroller
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 170 of 208 aug 12, 2016 csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 2. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. input data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 output data sckp input data output data sip sop sckp t kcy1 t kh1 t kl1 t sik1 t ksi1 t kso1
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 171 of 208 aug 12, 2016 ( notes , caution , and remarks are listed on the next page.) (7) communication at different potential (1.8 v, 2.5 v, 3 v) (csi mo de) (slave mode, sckp... external clock input) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time note 1 t kcy2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v 24 mhz < f mck 28/f mck ns 20 mhz < f mck 24 mhz 24/f mck ns 8 mhz < f mck 20 mhz 20/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 12/f mck ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v 24 mhz < f mck 40/f mck ns 20 mhz < f mck 24 mhz 32/f mck ns 16 mhz < f mck 20 mhz 28/f mck ns 8 mhz < f mck 16 mhz 24/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns f mck 4 mhz 12/f mck ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v 24 mhz < f mck 96/f mck ns 20 mhz < f mck 24 mhz 72/f mck ns 16 mhz < f mck 20 mhz 64/f mck ns 8 mhz < f mck 16 mhz 52/f mck ns 4 mhz < f mck 8 mhz 32/f mck ns f mck 4 mhz 20/f mck ns sckp high-/low-level width t kh2 , t kl2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v t kcy2 /2 - 24 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v t kcy2 /2 - 36 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v t kcy2 /2 - 100 ns sip setup time (to sckp ) note 2 t sik2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v 1/f mck + 40 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v 1/f mck + 40 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v 1/f mck + 60 ns sip hold time (from sckp ) note 3 t ksi2 1/f mck + 62 ns delay time from sckp to sop output note 4 t kso2 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 240 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 428 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r v = 5.5 k 2/f mck + 1146 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 172 of 208 aug 12, 2016 note 1. transfer rate in the snooze mode: max. 1 mbps note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and sckp pin, and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) remark 1. r b [ ]: communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10, 12, 13)) remark 4. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. also, communication at different potential cannot be perfo rmed during clock synchronous se rial communication with the slave select function. sckp sop user?s device sck si sip so v b r b rl78 microcontroller
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 173 of 208 aug 12, 2016 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 01, 10, 20, 30, 31), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0, 1, 3 to 5, 14) remark 2. csi01 of 48-, 52-, 64-pin products, and csi11 and csi21 cannot communicate at different potential. use other csi for communication at different potential. also, communication at different potential cannot be perfo rmed during clock synchronous se rial communication with the slave select function. sip sop sckp input data output data t kcy2 t kh2 t kl2 t sik2 t ksi2 t kso2 input data output data sip sop sckp t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 174 of 208 aug 12, 2016 (8) communication at different potentia l (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode unit min. max. sclr clock frequency f scl 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 100 note 1 khz 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 100 note 1 khz 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 100 note 1 khz hold time when sclr = ?l? t low 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1200 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 4600 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 4600 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 4650 ns hold time when sclr = ?h? t high 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 620 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 500 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 2700 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 2400 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 1830 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 175 of 208 aug 12, 2016 note 1. the value must also be equal to or less than f mck /4. note 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sdar pin and the n-ch open drain output (v dd tolerance (for the 30- to 52-pin products)/ev dd tolerance (for the 64- to 100-pin products)) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) (8) communication at different potentia l (1.8 v, 2.5 v, 3 v) (simplified i 2 c mode) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode unit min. max. data setup time (reception) t su:dat 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 1/f mck + 340 note 2 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 340 note 2 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 1/f mck + 760 note 2 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 760 note 2 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 1/f mck + 570 note 2 ns data hold time (transmission) t hd:dat 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 50 pf, r b = 2.7 k 0 770 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 0 770 ns 4.0 v ev dd0 5.5 v, 2.7 v v b 4.0 v, c b = 100 pf, r b = 2.8 k 0 1420 ns 2.7 v ev dd0 < 4.0 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 1420 ns 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 0 1215 ns
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 176 of 208 aug 12, 2016 simplified i 2 c mode connection diagram (during communication at different potential) simplified i 2 c mode serial transfer timing (durin g communication at different potential) remark 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage remark 2. r: iic number (r = 00, 01, 10, 11, 20, 30, 31), g: pim, pom number (g = 0, 1, 3 to 5, 14) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 01, 02, 10, 12, 13) rl78 microcontroller sdar sclr user?s device sda scl v b r b v b r b sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 177 of 208 aug 12, 2016 3.5.2 serial interface iica note 1. the first clock pulse is generat ed after this period when the star t/restart condition is detected. note 2. the maximum value (max.) of t hd: dat is during normal transfer and a wait st ate is inserted in the ack (acknowledge) timing. caution the values in the above table are applied even when bi t 2 (pior02) in the peripheral i/o redirection register 0 (pior0) is 1. at this time , the pin characteristics (i oh1 , i ol1 , v oh1 , v ol1 ) must satisfy the values in the redirect destination. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k fast mode: c b = 320 pf, r b = 1.1 k iica serial transfer timing remark n = 0, 1 (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions hs (high-speed main) mode unit standard mode fast mode min. max. min. max. scla0 clock frequency f scl fast mode: f clk 3.5 mhz ? ? 0 400 khz standard mode: f clk 1 mhz 0 100 ? ? khz setup time of restart condition t su: sta 4.7 0.6 s hold time note 1 t hd: sta 4.0 0.6 s hold time when scla0 = ?l? t low 4.7 1.3 s hold time when scla0 = ?h? t high 4.0 0.6 s data setup time (reception) t su: dat 250 100 ns data hold time (transmission) note 2 t hd: dat 03.45 0 0.9 s setup time of stop condition t su: sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s t su: dat t hd: sta restart condition sclan sdaan t low t high t su: sta t hd: sta t su: sto stop condition stop condition start condition t hd: dat t buf
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 178 of 208 aug 12, 2016 3.6 analog characteristics 3.6.1 a/d converte r characteristics note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (%fsr) to the full-scale value. note 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . note 4. refer to 3.6.2 temperature sensor characteristics/internal reference voltage characteristic . classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage (-) = av refm reference voltage (+) = v dd reference voltage (-) = v ss reference voltage (+) = v bgr reference voltage (-)= av refm ani0 to ani14 refer to 3.6.1 (1) .refer to 3.6.1 (3) . refer to 3.6.1 (4) . ani16 to ani20 refer to 3.6.1 (2) . internal reference voltage temperature sensor output voltage refer to 3.6.1 (1) .? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), ta rget pin: ani2 to ani14, internal referen ce voltage, and te mperature sensor output voltage (t a = -40 to +105c, 2.4 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 810bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 1.2 3.5 lsb conversion time t conv 10-bit resolution target pin: ani2 to ani14 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output volt- age (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 0.25 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.4 v av refp 5.5 v 1.5 lsb analog input voltage v ain ani2 to ani14 0 av refp v internal reference voltage output (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 4 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 4 v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 179 of 208 aug 12, 2016 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (%fsr) to the full-scale value. note 3. when ev dd0 av refp v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . note 4. when av refp < ev dd0 v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.20%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd . (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), target pin: ani16 to ani20 (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, 2.4 v av refp v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 810bit overall error note 1 ainl 10-bit resolution ev dd0 av refp = v dd notes 3, 4 2.4 v av refp 5.5 v 1.2 5.0 lsb conversion time t conv 10-bit resolution target ani pin: ani16 to ani20 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 10-bit resolution ev dd0 av refp = v dd notes 3, 4 2.4 v av refp 5.5 v 0.35 %fsr full-scale error notes 1, 2 e fs 10-bit resolution ev dd0 av refp = v dd notes 3, 4 2.4 v av refp 5.5 v 0.35 %fsr integral linearity error note 1 ile 10-bit resolution ev dd0 av refp = v dd notes 3, 4 2.4 v av refp 5.5 v 3.5 lsb differential linearity error note 1 dle 10-bit resolution ev dd0 av refp = v dd notes 3, 4 2.4 v av refp 5.5 v 2.0 lsb analog input voltage v ain ani16 to ani20 0 av refp and ev dd0 v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 180 of 208 aug 12, 2016 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. note 3. refer to 3.6.2 temperature sensor characteristics/internal reference voltage characteristic . (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage (-) = v ss (adrefm = 0), target pin: ani0 to ani14, ani16 to ani20, internal reference voltage, an d temperature sensor output volt- age (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v dd , reference voltage (-) = v ss ) parameter symbol conditions min. typ. max. unit resolution res 810bit overall error note 1 ainl 10-bit resolution 2.4 v v dd 5.5 v 1.2 7.0 lsb conversion time t conv 10-bit resolution target pin: ani0 to ani14, ani16 to ani20 3.6 v v dd 5.5 v 2.125 39 s 2.7 v v dd 5.5 v 3.1875 39 s 2.4 v v dd 5.5 v 17 39 s 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 3.6 v v dd 5.5 v 2.375 39 s 2.7 v v dd 5.5 v 3.5625 39 s 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 10-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr full-scale error notes 1, 2 e fs 10-bit resolution 2.4 v v dd 5.5 v 0.60 %fsr integral linearity error note 1 ile 10-bit resolution 2.4 v v dd 5.5 v 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.4 v v dd 5.5 v 2.0 lsb analog input voltage v ain ani0 to ani14 0 v dd v ani16 to ani20 0 ev dd0 v internal reference voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v bgr note 3 v temperature sensor output voltage (2.4 v v dd 5.5 v, hs (high-speed main) mode) v tmps25 note 3 v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 181 of 208 aug 12, 2016 note 1. excludes quantization error (1/2 lsb). note 2. this value is indicated as a ratio (% fsr) to the full-scale value. note 3. refer to 3.6.2 temperature sensor characteristics/internal reference voltage characteristic . note 4. when reference voltage (-) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage (-) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage (-) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage (-) = av refm . (4) when reference voltage (+) = intern al reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage (-) = av refm /ani1 (adrefm = 1), target pin: ani0, ani2 to ani14, ani16 to ani20 (t a = -40 to +105c, 2.4 v v dd 5.5 v, 1.6 v ev dd = ev dd1 v dd , v ss = ev ss0 = ev ss1 = 0 v, reference voltage (+) = v bgr note 3 , reference voltage (-) = av refm = 0 v note 4 , hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution res 8 bit conversion time t conv 8-bit resolution 2.4 v v dd 5.5 v 17 39 s zero-scale error notes 1, 2 e zs 8-bit resolution 2.4 v v dd 5.5 v 0.60 % fsr integral linearity error note 1 ile 8-bit resolution 2.4 v v dd 5.5 v 2.0 lsb differential linearity error note 1 dle 8-bit resolution 2.4 v v dd 5.5 v 1.0 lsb analog input voltage v ain 0 v bgr note 3 v
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 182 of 208 aug 12, 2016 3.6.2 temperature sensor characteristics/internal reference voltage characteristic 3.6.3 d/a converter characteristics (t a = -40 to +105c, 2.4 v v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature -3.6 mv/ c operation stabilization wait time t amp 5 s (t a = -40 to +105c, 2.4 v ev ss0 = ev ss1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8bit overall error ainl rload = 4 m 2.4 v v dd 5.5 v 2.5 lsb rload = 8 m 2.4 v v dd 5.5 v 2.5 lsb settling time t set cload = 20 pf 2.7 v v dd 5.5 v 3 s 2.4 v v dd < 2.7 v 6 s
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 183 of 208 aug 12, 2016 3.6.4 comparator note not usable in sub-clock operation or stop mode. 3.6.5 por circui t characteristics note 1. however, when the operating voltage falls while the lvd is off, enter stop mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 3.4 ac characteristics. note 2. minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit input voltage range ivref 0ev dd0 - 1.4 v ivcmp -0.3 ev dd0 + 0.3 v output delay td v dd = 3.0 v input slew rate > 50 mv/ s comparator high-speed mode, standard mode 1.2 s comparator high-speed mode, window mode 2.0 s comparator low-speed mode, standard mode 3.0 5.0 s high-electric-potential reference voltage vtw+ comparator high-speed mode, window mode 0.76 v dd v low-electric-potential ref- erence voltage vtw- comparator high-speed mode, window mode 0.24 v dd v operation stabilization wait time t cmp 100 s internal reference voltage note v bgr 2.4 v v dd 5.5 v, hs (high-speed main) mode 1.38 1.45 1.50 v (t a = -40 to +105c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power on/down reset threshold v por voltage threshold on v dd rising 1.45 1.51 1.57 v v pdr voltage threshold on v dd falling note 1 1.44 1.50 1.56 v minimum pulse width note 2 t pw 300 s t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 184 of 208 aug 12, 2016 3.6.6 lvd circui t characteristics (1) reset mode and interrupt mode (t a = -40 to +105c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit voltage detection threshold supply voltage level v lvd0 rising edge 3.90 4.06 4.22 v falling edge 3.83 3.98 4.13 v v lvd1 rising edge 3.60 3.75 3.90 v falling edge 3.53 3.67 3.81 v v lvd2 rising edge 3.01 3.13 3.25 v falling edge 2.94 3.06 3.18 v v lvd3 rising edge 2.90 3.02 3.14 v falling edge 2.85 2.96 3.07 v v lvd4 rising edge 2.81 2.92 3.03 v falling edge 2.75 2.86 2.97 v v lvd5 rising edge 2.70 2.81 2.92 v falling edge 2.64 2.75 2.86 v v lvd6 rising edge 2.61 2.71 2.81 v falling edge 2.55 2.65 2.75 v v lvd7 rising edge 2.51 2.61 2.71 v falling edge 2.45 2.55 2.65 v minimum pulse width t lw 300 s detection delay time 300 s
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 185 of 208 aug 12, 2016 3.6.7 power supply voltage rising slope characteristics caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 3.4 ac characteristics. (2) interrupt & reset mode (t a = -40 to +105c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit voltage detection threshold v lvdd0 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 v v lvdd1 lvis1, lvis0 = 1, 0 rising release reset voltage 2.81 2.92 3.03 v falling interrupt voltage 2.75 2.86 2.97 v v lvdd2 lvis1, lvis0 = 0, 1 rising release reset voltage 2.90 3.02 3.14 v falling interrupt voltage 2.85 2.96 3.07 v v lvdd3 lvis1, lvis0 = 0, 0 rising release reset voltage 3.90 4.06 4.22 v falling interrupt voltage 3.83 3.98 4.13 v (t a = -40 to +105c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 186 of 208 aug 12, 2016 3.7 ram data retention characteristics note the value depends on the por detection voltage. when the volt age drops, the ram data is retained before a por reset is effected, but ram data is not retained when a por reset is effected. 3.8 flash memory programming characteristics note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. note 2. when using flash memory programmer and renes as electronics self-programming library note 3. these are the characteristics of the fl ash memory and the results obtained from reliability testing by renesas electronics corporation. note 4. this temperature is the average value at which data are retained. 3.9 dedicated flash memory programmer communication (uart) (t a = -40 to +105c, v ss = 0v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v (t a = -40 to +105c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit system clock frequency f clk 2.4 v v dd 5.5 v 1 32 mhz number of code flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85c note 4 1,000 times number of data flash rewrites notes 1, 2, 3 retained for 1 year t a = 25c 1,000,000 retained for 5 years t a = 85c note 4 100,000 retained for 20 years t a = 85c note 4 10,000 (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps v dd stop instruction execution standby release signal (interrupt request) stop mode ram data retention operation mode v dddr
rl78/g14 3. electrical specificati ons (g: industrial applications t a = -40 to +105 c) r01ds0053ej0330 rev. 3.30 page 187 of 208 aug 12, 2016 3.10 timing of entry to flash memory programming modes <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial comm unication settings within 100 ms from when the external resets end. t su : how long from when the tool0 pin is plac ed at the low level until a pin reset ends t hd: how long to keep the tool0 pin at the low level from when the external resets end (excluding the processing time of the fi rmware to control the flash memory) (t a = -40 to +105c, 2.4 v ev dd0 = ev dd1 v dd 5.5 v, v ss = ev ss0 = ev ss1 = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1ms reset tool0 <1> <2> <3> t su <4> t suinit 723 s + t hd processing time 00h reception (toolrxd, tooltxd mode)
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 188 of 208 aug 12, 2016 4. package drawings 4.1 30-pin products r5f104aaasp, r5f104acasp, r5f104adasp, r5f104aeasp, r5f104afasp, r5f104agasp r5f104aadsp, r5f104acdsp, r5f104addsp, r5f104aedsp, r5f104afdsp, r5f104agdsp r5f104aagsp, r5f104acgsp, r5f104adgsp, r5f104aegsp, r5f104afgsp, r5f104aggsp jeita package code renesas code previous code mass (typ.) [g] p-lssop30-0300-0.65 plsp0030jb-b s30mc-65-5a4-3 0.18 s s h j t i g d e f c b k p l u n item b c i l m n a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 p 0.2 0.10 9.85 p 0.15 0.17 p 0.03 0.1 p 0.05 0.24 1.3 p 0.1 8.1 p 0.2 1.2 0.08 0.07 1.0 p 0.2 3 o 5 o 3 o 0.25 0.6 p 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2012 renesas electronics corporation. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 189 of 208 aug 12, 2016 4.2 32-pin products r5f104baana, r5f104bcana, r5f104bdana, r5f104beana, r5f104bfana, r5f104bgana r5f104badna, r5f104bcdna, r5f104bddna, r5f104bedna, r5f104bfdna, r5f104bgdna r5f104bagna, r5f104bcgna, r5f104bdgna, r5f104begna, r5f104bf gna, r5f104bggna 2012 renesas electronics corporation. all rights reserved. s y e lp s x ba b m a d e 24 16 17 8 9 1 32 a s b a s d2 e2 25 detail of a part exposed die pad item d2 e2 a min nom max 3.45 3.50 exposed die pad variations 3.55 min nom max 3.45 3.50 3.55 jeita package code renesas code previous code mass (typ.) [g] p-hwqfn32-5x5-0.50 pwqn0032kb-a p32k8-50-3b4-4 0.06 d e a b e lp 0.40 0.50 5.00 5.00 0.75 0.25 referance symbol min nom max dimension in millimeters 0.70 0.18 0.80 0.30 0.30 0.50 x 0.05 4.95 4.95 5.05 5.05 y 0.05
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 190 of 208 aug 12, 2016 r5f104baafp, r5f104bcafp, r5f104bdafp, r5 f104beafp, r5f104bfafp, r5f104bgafp r5f104badfp, r5f104bcdfp, r5f104bddfp, r5f104bedfp, r5f104bfdfp, r5f104bgdfp r5f104bagfp, r5f104bcgfp, r5f104bdgfp, r5f104begfp, r5f104bfgfp, r5f104bggfp 2012 renesas electronics corporation. all rights reserved. 0.145 0.055 (unit:mm) item dimensions d e hd he a a1 a2 7.00 0.10 7.00 0.10 9.00 0.20 9.00 0.20 1.70 max. 0.10 0.10 1.40 c e x y 0.80 0.20 0.10 l 0.50 0.20 0 to 8 0.37 0.05 b note 1.dimensions 1 and 2 do not include mold flash. 2.dimension 3 does not include trim offset. y e x b m l c hd he a1 a2 a d e detail of lead end 8 16 1 32 9 17 25 24 2 1 3 jeita package code renesas code previous code mass (typ.) [g] p-lqfp32-7x7-0.80 plqp0032gb-a p32ga-80-gbt-1 0.2
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 191 of 208 aug 12, 2016 4.3 36-pin products r5f104caala, r5f104ccala, r5f104cdala, r5 f104ceala, r5f104cfala, r5f104cgala r5f104cagla, r5f104ccgla, r5f104cdgla, r5f104cegla, r5f104cfgla, r5f104cggla jeita package code renesas code previous code mass (typ.) [g] p-wflga36-4x4-0.50 pwlg0036ka-a p36fc-50-aa4-2 0.023 item dimensions d e w e a b x y y1 zd ze 4.00 p 0.10 4.00 p 0.10 0.05 0.20 0.69 p 0.07 0.08 0.50 0.24 p 0.05 (unit:mm) 0.20 0.75 0.75 s y1 s a s y s x 32x b a b m e s wb zd ze index mark b c a s wa d e e 1 2 e f dc b a 3 4 5 6 c d detail detail e detail b 0.34 p 0.05 0.55 0.70 p 0.05 0.55 p 0.05 0.70 p 0.05 0.55 p 0.05 0.75 f f 0.75 0.55 0.55 r0.17 p 0.05 r0.17 p 0.05 r0.12 p 0.05 r0.12 p 0.05 r0.275 p 0.05 r0.35 p 0.05 0.75 0.55 p 0.05 0.70 p 0.05 0.55 0.75 0.55 p 0.05 0.70 p 0.05 (land pad) (aperture of solder resist) d 2.90 2.90 2012 renesas electronics corporation. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 192 of 208 aug 12, 2016 4.4 40-pin products r5f104eaana, r5f104ecana, r5f104edana, r5f104eeana, r5f104efana, r5f104egana, r5f104ehana r5f104eadna, r5f104ecdna, r5f104eddna, r5f104eedna, r5f104efdna, r5f104egdna, r5f104ehdna r5f104eagna, r5f104ecgna, r5f104edgna, r5f104eegna, r5f104ef gna, r5f104eggna, r5f104ehgna 2012 renesas electronics corporation. all rights reserved. jeita package code renesas code previous code mass (typ.) [g] p-hwqfn40-6x6-0.50 pwqn0040kc-a p40k8-50-4b4-4 0.09 detail of a part s y e lp s x ba b m a d e 30 20 21 10 11 1 40 a s b a s d2 e2 31 exposed die pad item d2 e2 a min nom max 4.45 4.50 exposed die pad variations 4.55 min nom max 4.45 4.50 4.55 d e a b e lp 0.40 0.50 6.00 6.00 0.75 0.25 referance symbol min nom max dimension in millimeters 0.70 0.18 0.80 0.30 0.30 0.50 x 0.05 5.95 5.95 6.05 6.05 y 0.05
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 193 of 208 aug 12, 2016 4.5 44-pin products r5f104faafp, r5f104fcafp, r5f104fdafp, r5f104feafp, r5f104ffafp, r5f104fgafp, r5f104fhafp, r5f104fjafp r5f104fadfp, r5f104fcdfp, r5f104fddfp, r5f104fedfp, r5f104ffdfp, r5f104fgdfp, r5f104fhdfp, r5f104fjdfp r5f104fagfp, r5f104fcgfp, r5f104fdgfp, r5f104fegfp, r5f104ffgfp, r5f104fggfp, r5f104fhgfp, r5f104fjgfp jeita package code renesas code previous code mass (typ.) [g] p-lqfp44-10x10-0.80 plqp0044gc-a p44gb-80-ues-2 0.36 s y e s x b m q l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 0.055 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 p 0.20 10.00 p 0.20 12.00 p 0.20 12.00 p 0.20 1.60 max. 0.10 p 0.05 1.40 p 0.05 0.25 c q e x y zd ze 0.80 0.20 0.10 1.00 1.00 l lp l1 0.50 0.60 p 0.15 1.00 p 0.20 3 o 5 o 3 o note each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 0.37 0.08 0.07 b 11 22 1 44 12 23 34 33 2012 renesas electronics corporation. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 194 of 208 aug 12, 2016 4.6 48-pin products r5f104gaafb, r5f104gcafb, r5f104gdafb, r5f104geafb, r5f104gfafb, r5f104ggafb, r5f104ghafb, r5f104gjafb r5f104gadfb, r5f104gcdfb, r5f104gddfb, r5f104gedfb, r5f104gfdfb, r5f104ggdfb, r5f104ghdfb, r5f104gjdfb r5f104gagfb, r5f104gcgfb, r5f104gdgfb, r5f104gegfb, r5f104gfgfb, r5f104gggfb, r5f104ghgfb, r5f104gjgfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp48-7x7-0.50 plqp0048kf-a p48ga-50-8eu-1 0.16 s y e s x b m q l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 0.055 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 p 0.20 7.00 p 0.20 9.00 p 0.20 9.00 p 0.20 1.60 max. 0.10 p 0.05 1.40 p 0.05 0.25 c q e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 p 0.15 1.00 p 0.20 3 o 5 o 3 o note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 p 0.05 b 12 24 1 48 13 25 37 36 2012 r el t i c ti all i ht d
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 195 of 208 aug 12, 2016 r5f104gkafb, r5f104glafb r5f104gkgfb, r5f104glgfb terminal cross section b 1 c 1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. detail f l 1 c a l a 1 a 2 * 3 f 48 37 36 25 24 13 12 1 * 1 * 2 x index mark z e z d b p e h e h d d e previous code jeita package code renesas code plqp0048kb-a 48p6q-a mass[typ.] 0.2g p-lfqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 196 of 208 aug 12, 2016 r5f104gaana, r5f104gcana, r5f104gdana, r5f104geana, r5f104gfana, r5f104ggana, r5f104ghana, r5f104gjana r5f104gadna, r5f104gcdna, r5f104gddna, r5f104gedna, r5f104gfdna, r5f104ggdna, r5f104ghdna, r5f104gjdna r5f104gagna, r5f104gcgna, r5f104gdgna, r5f104gegna, r5f104g fgna, r5f104gggna, r5f104ghgna, r5f104gjgna r5f104gkana, r5f104glana r5f104gkgna, r5f104glgna 2012 renesas electronics corporation. all rights reserved. detail of a part s y e lp s x ba b m a d e 36 37 24 25 12 13 1 48 a s b a s d2 e2 exposed die pad item d2 e2 a min nom max 5.45 5.50 exposed die pad variations 5.55 min nom max 5.45 5.50 5.55 jeita package code renesas code previous code mass (typ.) [g] p-hwqfn48-7x7-0.50 pwqn0048kb-a 48pjn-a p48k8-50-5b4-5 0.13 d e a b e lp 0.40 0.50 7.00 7.00 0.75 0.25 referance symbol min nom max dimension in millimeters 0.70 0.18 0.80 0.30 0.30 0.50 x 0.05 6.95 6.95 7.05 7.05 y 0.05
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 197 of 208 aug 12, 2016 4.7 52-pin products r5f104jcafa, r5f104jdafa, r5f104jeafa, r5f104 jfafa, R5F104JGAfa, r5 f104jhafa, r5f104jjafa r5f104jcdfa, r5f104jddfa, r5f104jedfa, r5f104jfdfa, r5f104jgdfa, r5f104jhdfa, r5f104jjdfa r5f104jcgfa, r5f104jdgfa, r5f104jegfa, r5f104 jfgfa, r5f104jggfa, r5f104jhgfa, r5f104jjgfa y e x b m l c hd he a1 a2 a d e 0.145 0.055 (unit:mm) item dimensions d e hd he a a1 a2 10.00 0.10 10.00 0.10 12.00 0.20 12.00 0.20 1.70 max. 0.10 0.05 1.40 c e x y 0.65 0.13 0.10 l 0.50 0.15 0 to 8 detail of lead end 0.32 0.05 b 13 26 1 52 14 27 40 39 2 1 3 2012 renesas electronics corporation. all rights reserved. note 1.dimensions 1 and 2 do not include mold flash. 2.dimension 3 does not include trim offset. jeita package code renesas code previous code mass (typ.) [g] p-lqfp52-10x10-0.65 plqp0052ja-a p52gb-65-gbs-1 0.3
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 198 of 208 aug 12, 2016 4.8 64-pin products r5f104lcafa, r5f104ldafa, r5f104leafa, r5f104lf afa, r5f104lgafa, r5f1 04lhafa, r5f104ljafa r5f104lcdfa, r5f104lddfa, r5f104ledfa, r5f104 lfdfa, r5f104lgdfa, r5f104lhdfa, r5f104ljdfa r5f104lcgfa, r5f104ldgfa, r5f104legfa, r5f104lfgfa, r5f104lggfa, r5f104lhgfa, r5f104ljgfa r5f104lkafa, r5f104llafa r5f104lkgfa, r5f104llgfa jeita package code renesas code previous code mass (typ.) [g] p-lqfp64-12x12-0.65 plqp0064ja-a p64gk-65-uet-2 0.51 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end q l c lp hd he zd ze l1 a1 a2 a d e 16 32 1 64 17 33 49 48 s y e s x b m a3 s 0.145 0.055 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 p 0.20 12.00 p 0.20 14.00 p 0.20 14.00 p 0.20 1.60 max. 0.10 p 0.05 1.40 p 0.05 0.25 c q e x y zd ze 0.65 0.13 0.10 1.125 1.125 l lp l1 0.50 0.60 p 0.15 1.00 p 0.20 3 o 5 o 3 o 0.32 0.08 0.07 b 2012 renesas electronics corpo ration. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 199 of 208 aug 12, 2016 r5f104lkafb, r5f104llafb r5f104lkgfb, r5f104llgfb terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lfqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 200 of 208 aug 12, 2016 r5f104lcafb, r5f104ldafb, r5f104leafb, r5f104lfafb, r5f104lgafb, r5f104lhafb, r5f104ljafb r5f104lcdfb, r5f104lddfb, r5f104ledfb, r5f104lfdfb, r5f104lgdfb, r5f104lhdfb, r5f104ljdfb r5f104lcgfb, r5f104ldgfb, r5f104legfb, r5f104lfgfb, r5f104lggfb, r5f104lhgfb, r5f104ljgfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp64-10x10-0.50 plqp0064kf-a p64gb-50-ueu-2 0.35 s y e s x b m q l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 0.055 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 p 0.20 10.00 p 0.20 12.00 p 0.20 12.00 p 0.20 1.60 max. 0.10 p 0.05 1.40 p 0.05 0.25 c q e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 p 0.15 1.00 p 0.20 3 o 5 o 3 o note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 p 0.05 b 16 32 1 64 17 33 49 48 2012 renesas electronics corporatio n. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 201 of 208 aug 12, 2016 r5f104lcala, r5f104ldala, r5f104leala, r5f104lf ala, r5f104lgala, r5f1 04lhala, r5f104ljala r5f104lkala, r5f104llala r5f104lcgla,r5f104ldgla, r5f104legla, r5f104lfg la, r5f104lggla, r5f104lhgla, r5f104ljgla r5f104lkgla, r5f104llgla 64-pin plastic flga (5x5) e w 5.00 o 0.10 0.20 y 0.20 0.08 y1 zd 0.75 0.05 x d 5.00 o 0.10 a 0.69 o 0.07 b 0.25 o 0.04 p64fc-50-an5 ze 0.75 s b s w s y y1 e 0.50 index mark w sa zd ze a b s a b e xs 8 7 6 5 4 3 2 1 b c d e f g h a c d c d detail detail e detail m 60x a b item dimensions (unit:mm) 3.90 3.90 b 0.34 o 0.03 0.55 0.70 o 0.03 0.55 o 0.04 0.70 o 0.03 0.55 o 0.04 0.75 0.75 0.55 0.55 r0.17 o 0.015 r0.17 o 0.015 r0.125 o 0.02 r0.125 o 0.02 r0.275 o 0.02 r0.35 o 0.015 0.75 0.55 o 0.04 0.70 o 0.03 0.55 0.75 0.55 o 0.04 0.70 o 0.03 (land pad) (aperture of solder resist) e e d 2011 renesas electronics corporation. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 202 of 208 aug 12, 2016 r5f104lcafp, r5f104ldafp, r5f104leafp, r5f104lfafp, r5f104lgafp, r5f104lhafp, r5f104ljafp r5f104lcdfp, r5f104lddfp, r5f104ledfp, r5f104lfdfp, r5f104lgdfp, r5f104lhdfp, r5f104ljdfp r5f104lcgfp, r5f104ldgfp, r5f104legfp, r5f104lfgfp, r5f104lggfp, r5f104lhgfp, r5f104ljgfp y e x b m hd he a1 a2 a d e 0.125 (unit:mm) item dimensions d e hd he a a1 a2 14.00 0.10 14.00 0.10 16.00 0.20 16.00 0.20 1.70 max. 0.10 0.10 1.40 c l 0.50 0.20 0 to 8 detail of lead end 0.37 b 16 32 1 64 17 33 49 48 2 1 3 2012 renesas electronics corporation. all rights reserved. ? 0.02 + 0.05 ? 0.05 + 0.08 l c note 1.dimensions 1 and 2 do not include mold flash. 2.dimension 3 does not include trim offset. jeita package code renesas code previous code mass (typ.) [g] p-lqfp64-14x14-0.80 plqp0064ga-a p64gc-80-gbw-1 0.7 0.80 0.20 0.10 e x y
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 203 of 208 aug 12, 2016 4.9 80-pin products r5f104mfafb, r5f104mgafb, r5f104mhafb, r5f104mjafb r5f104mfdfb, r5f104mgdfb, r5f104mhdfb, r5f104mjdfb r5f104mfgfb, r5f104mggfb, r5f104mhgfb, r5f104mjgfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp80-12x12-0.50 plqp0080ke-a p80gk-50-8eu-2 0.53 s y e s x b m q l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 0.055 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 p 0.20 12.00 p 0.20 14.00 p 0.20 14.00 p 0.20 1.60 max. 0.10 p 0.05 1.40 p 0.05 0.25 c q e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 p 0.15 1.00 p 0.20 3 o 5 o 3 o note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 p 0.05 b 20 40 1 80 21 41 61 60 2012 renesas electronics corporation. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 204 of 208 aug 12, 2016 r5f104mkafb, r5f104mlafb r5f104mkgfb, r5f104mlgfb detail f c a l 1 l a 1 a 2 index mark * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lfqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 12.1 12.0 11.9 d 12.1 12.0 11.9 e 1.4 a 2 14.2 14.0 13.8 14.2 14.0 13.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 205 of 208 aug 12, 2016 r5f104mfafa, r5f104mgafa, r5f104mhafa, r5f104mjafa r5f104mfdfa, r5f104mgdfa, r5f104mhdfa, r5f104mjdfa r5f104mfgfa, r5f104mggfa, r5f104mhgfa, r5f104mjgfa r5f104mkafa, r5f104mlafa r5f104mkgfa, r5f104mlgfa 2012 renesas electronics corporation. all rights reserved. jeita package code renesas code previous code mass (typ.) [g] p-lqfp80-14x14-0.65 plqp0080jb-e p80gc-65-ubt-2 0.69 d e hd he a a2 bp c lp q x l1 0.13 0.886 14.00 14.00 17.20 17.20 1.40 0.10 referance symbol min nom max dimension in millimeters a1 0.05 1.35 0.26 1.70 0.20 1.45 0.38 13.80 13.80 17.00 17.00 14.20 14.20 17.40 17.40 0.10 0.20 e 0.65 0.736 1.036 1.60 0 n 8 n a3 0.25 0.125 0.32 0.145 l 0.80 1.40 1.80 zd 0.825 ze 0.825 3 n y s y e s x bp m l c lp hd he zd ze l1 a1 a2 a e a3 s detail of lead end 20 40 1 80 21 41 d a b ab 61 60
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 206 of 208 aug 12, 2016 4.10 100-pin products r5f104pfafb, r5f104pgafb, r5f104phafb, r5f104pjafb r5f104pfdfb, r5f104pgdfb, r5f104phdfb, r5f104pjdfb r5f104pfgfb, r5f104pggfb, r5f104phgfb, r5f104pjgfb s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 p 0.20 14.00 p 0.20 16.00 p 0.20 16.00 p 0.20 1.60 max. 0.10 p 0.05 1.40 p 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.00 1.00 l lp l1 0.50 0.60 p 0.15 1.00 p 0.20 3 o 3 o 5 o detail of lead end 0.22 0.055 0.045 b 25 50 1 100 26 51 75 76 p 0.05 a b ab jeita package code renesas code previous code mass (typ.) [g] p-lfqfp100-14x14-0.50 plqp0100ke-a p100gc-50-gbr-1 0.69 2012 renesas electronics corporation. all rights reserved.
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 207 of 208 aug 12, 2016 r5f104pkafb, r5f104plafb r5f104pkgfb, r5f104plgfb terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lfqfp100-14x14-0.50 e y s s
rl78/g14 4. package drawings r01ds0053ej0330 rev. 3.30 page 208 of 208 aug 12, 2016 r5f104pfafa, r5f104pgafa, r5f104phafa, r5f104pjafa r5f104pfdfa, r5f104pgdfa, r5f104phdfa, r5f104pjdfa r5f104pfgfa, r5f104pggfa, r5f104phgfa, r5f104pjgfa r5f104pkafa, r5f104plafa r5f104pkgfa, r5f104plgfa b s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.07 0.08 0.055 0.045 0.25 c e x y zd ze 0.65 0.13 0.10 0.575 0.825 l lp l1 0.50 0.60 0.15 5 3 1.00 0.20 3 detail of lead end 0.32 b 30 50 1 100 31 51 81 80 a ab jeita package code renesas code previous code mass (typ.) [g] p-lqfp100-14x20-0.65 plqp0100jc-a p100gf-65-gbn-1 0.92 2012 renesas electronics corporation . all rights reserved.
c - 1 rl78/g14 datasheet rev. date description page summary 0.01 feb 10, 2011 ? first edition issued 0.02 may 01, 2011 1 to 2 1.1 features revised 3 1.2 ordering information revised 4 to 13 1.3 pin configuration (top view) revised 14 1.4 pin identif ication revised 15 to 17 1.5.1 30-pin products to 1.5.3 36-pin products revised 23 to 26 1.6 outline of functions revised 0.03 jul 28, 2011 1 1.1 features revised 1.00 feb 21, 2012 1 to 40 1. outline revised 41 to 97 2. electrical specifications added 2.00 oct 25, 2013 1 modification of 1.1 features 3 to 8 modification of 1.2 ordering information 9 to 22 modification of package type in 1.3 pin configuration (top view) 34 to 43 modification of description of subsystem clo ck in 1.6 outline of functions 34 to 43 modification of description of ti mer output in 1.6 outline of functions 34 to 43 modification of error of data tran sfer controller in 1.6 outline of functions 34 to 43 modification of error of event lin k controller in 1.6 outline of functions 45, 46 modification of description of tables in 2.1 absolute maximum ratings 47 modification of tables, notes, cauti ons, and remarks in 2.2 oscillator characteristics 48 modification of error of conditions of high level input voltage in 2.3.1 pin characteristics 49 modification of error of conditions of low level output voltage in 2.3.1 pin characteristics 53 to 62 modification of notes and remar ks in 2.3.2 supply current characteristics 65, 66 addition of minimum instruction execut ion time during main system clock operation 67 to 69 addition of ac timing test points 70 to 97 addition of ls mode and lv mode characteristics in 2.5.1 serial array unit 98 to 101 addition of ls mode and lv mode char acteristics in 2.5.2 serial interface iica 102 to 105 addition of characteristics about conversi on of internal reference voltage and temperature sensor in 2.6.1 a/d converter characteristics 107 addition of characteristic in 2.6.4 comparator 107 deletion of detection delay in 2.6.5 por circuit characteristics 109 modification of 2.6.7 power supply voltage rising slope characteristics 110 modification of 2.7 data memory stop mode low supply voltage data retention characteristics 110 addition of characteristic in 2.8 fl ash memory programming characteristics 111 addition of description in 2.10 timing for switching flash memory programming modes revision history
revision history rl78/g14 datasheet c - 2 2.00 oct 25, 2013 112 to 169 addition of chapter 3 electrical specifications 171 to 187 modification of 4.1 30-pin products to 4.10 100-pin products 3.00 feb 07, 2014 all addition of products with maximum 512 kb flash rom and 48 kb ram 1 modification of 1.1 features 2 modification of rom, ram capacities and addition of note 3 3 modification of figure 1 - 1 part number, memory size, and package of rl78/g14 6 to 8 addition of part number 15, 16 modification of 1.3.6 48-pin products 17 modification of 1.3.7 52-pin products 18, 19 modification of 1.3.8 64-pin products 20 modification of 1.3.9 80-pin products 21, 22 modification of 1.3.10 100-pin products 35, 37, 39, 41, 43, 45, 47 modification of operating ambient tem perature in 1.6 outline of functions 42, 43 addition of table of 48-pin, 52-pin, 64-pin products (code flash memory 384 kb to 512 kb) 46, 47 addition of table of 80-pin, 100-pin products (code flash memory 384 kb to 512 kb) 65 to 68 addition of (3) flash rom: 384 to 512 kb of 48- to 100-pin products 118 modification of 2.7 data memo ry retention characteristics 137 to 140 addition of (3) flash rom: 384 to 512 kb of 48- to 100-pin products 180 modification of 3.7 data memo ry retention characteristics 189, 190 addition and modification of 4.6 48-pin products 191 modification of 4.7 52-pin products 193 to 195 addition and modification of 4.8 64-pin products 198, 199 addition and modification of 4.9 80-pin products 201, 202 addition and modification of 4.10 100-pin products 3.20 jan 05, 2015 p.2 deletion of r5f104jk and r5f1 04jl from the list of rom and ram capacities and modification of note p.6 deletion of ordering pa rt numbers of r5f104jk and r5f104jl from 52-pin plastic lqfp package in 1.2 ordering information p.6 to 8 deletion of note 2 in 1.2 ordering information p.17 deletion of note 2 in 1.3.7 52-pin products p.36, 39, 42, 45, 48, 50, 52 modification of description in 1.6 outline of functions p.46, 48 deletion of description of 52-pin in 1.6 outline of functions p.47 modification of note of 1.6 outline of functions p.62, 64, 66, 68, 70, 72 modification of specifications in 2. 3.2 supply current characteristics rev. date description page summary
revision history rl78/g14 datasheet c - 3 3.20 jan 05, 2015 p.135, 137, 139, 141, 143, 145 modification of specifications in 3. 3.2 supply current characteristics p.197 modification of part nu mber in 4.7 52-pin products 3.30 aug 12, 2016 p.143, 145 addition of maximum values in (3) flash rom: 384 to 512 kb of 48- to 100-pin products of 3.3.2 supply current characteristics rev. date description page summary superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from s ilicon storage technology, inc. all trademarks and registered trademarks ar e the property of their respective owners.
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics do es not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property right s of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, e specially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have spec ific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or otherwis e places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas e lectronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this documen t or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subs idiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 9251 yonge street, suite 8309 richmond hill, ontario canada l4c 9t3 tel: +1-905-237-2004 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal ii stage, indiranagar, bangalore, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2016 renesas electronics corporation. all rights reserved. colophon 5.0

▲Up To Search▲

Price & Availability of R5F104JGA

	To Download R5F104JGA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .